Self-correcting memory arrives at last
Sadly we speak here of NAND Flash, not one's brain
Micron is putting error correction code (ECC) in its NAND chips to combat increased error rates as NAND process sizes shrink.
The company says that as NAND process sizes decrease to 20nm and then become even smaller, the bit error rates will rise, requiring NAND controllers in mobile phones and other flash-using devices to devote more processor cycles to detecting and recovering from errors.
It has developed ClearNAND technology which puts ECC functionality into the NAND chips and relieves the host processor of much ECC work. The first implementation is with Micron's 25nm multi-level cell (MLC) NAND products and comes in two versions.
Standard ClearNAND comes with the 8GB - 32GB chips, which are targeted at consumer electronic devices like portable media players. An Enhanced ClearNAND option is said by Micron to add specific but unidentified features to increase performance and reliability for high-capacity designs in enterprise and other computing applications.
We should think – or so El Reg supposes – of storage array solid state drive (SSD) tiers, banks of server cache and that sort of thing [Quite so - Ed]. Micron is making this available for its 16GB - 64GB products. NAND chips using both versions still have what Micron calls a traditional raw NAND interface.
Micron is expected to announce a process shrink down to the 20nm level in the next few months.
We could well imagine that on-chip ECC will become more important as 2-bit MLC progresses to 3- and 4-bit MLC where the number of cells and process shrinks could combine to increase the bit error rate substantially. Affordability, performance, reliability and endurance are going to be key to the acceptance of 2-, 3- and 4-bit MLC in flash-using devices and Micron has just added a reliability enhancement to its MLC products. Expect its competitors to follow suit. ®
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