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GlobalFoundries says Intel process squeezes chip devs

Future chips: extreme, ultraviolet & metal

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'Intel and TSMC have it backwards'

Lithography, however, isn't the only challenge facing designers of ever-shrinking process-node technologies. There's also the fact that as chip elements get smaller and smaller, current leakage at transistor gates can cause fatal problems — fatal to chip performance, that is.

The solution here is to use materials other than traditional polysilicon when building transistor gates — and Intel took an early lead in this sphere when it introduced its high-k metal gate technology in its 45nm "Penryn" line, launched in November 2007.

But there's more than one way to gain the low current-leakage advantages provided by high-k metal gate–based chips. Bartlett drew a distinction between the high-k metal-gate technology to be used by GlobalFoundries and that which is now employed by Intel and soon to be introduced by the Taiwanese chip-baking giant TSMC — although, as The Reg has noted before, GlobalFoundries and its allies in the joint development alliance (JDA) prefer the term "HKMG".

Stripped to its basics, the distinction is that the JDA chip-bakers use what's called a "gate-first" manufacturing process, while Intel and TSMC's process is "gate-last", also known as "gate-replacement". The first/last difference refers to at which point in the manufacturing process that the gate itself is created, and replacement refers to the technique used in its manufacturing.

Debate continues as to which method is preferable, but the arguments essentially boil down to the gate-first method being more in line with that of good ol' fashioned polysilicon-gate creation, and therefore simpler, more conducive to existing chip designs, and arguably more scalable.

The gate-last proponents concede that their method is more complex, but since it doesn't involve subjecting the gate material to high temperatures, designers have a wider range of materials from which to choose, allowing for better optimization. Intel also claims (PDF) that the gate-last scheme can be a boon to strained-silicon enhancements.

Bartlett, as might have been guessed, touted the advantages of gate-first HKMG technology. One major advantage, he claimed, is that the gate-first method not only can produce chips of comparable performance to that of gate-last chips, but can do so in a smaller-sized die. And, of course, the smaller the die, the greater the yield per wafer, and thus the lower the cost per chip.

What's more, a gate-first design doesn't require a massive redesign project, since the manufacturing process is similar to that of existing polysilicon-gate chips.

"The promise of a gate-first implementation is, in fact, a more flexible and a more traditional design style," Bartlett said. "It was our very clear, stated strategy to not force the implementation of a new material and a new design style upon our customer base. There's enough technical risk associated with just the introduction of high-k metal gate that trying to ask our customer base to completely change their approach to how they design products was not the right approach."

Playing to his audience of chip designers who were either GlobalFoundries customers or potential customers, Bartlett reminded them: "This really is the key point to a gate-first implementation for high-k metal gate: maintaining the same degree of flexibility. So we support bidirectional poly-routing, we support jogs, and those are things that many of you as customers can continue to do, versus a gate-last implementation where you can no longer do those things."

The cost savings are not insignificant, according to Barlett. "So how does that show up in the marketplace?" he asked rhetorically, then answered: "Well, it shows up in your P&L statement." Bartlett argued that over a four-year product cycle that would cost $500m in a gate-last implementation, GlobalFoundies' gate-first manufacturing could save its customers a cool $75m, simply by needing to run fewer wafers to produce the same number of chips.

Gate-last Intel, of course, is its own customer, and so the cost savings that might be experienced by a third-party customer of a gate-first foundry is not a prime motivator. Saving money is a wonderful thing, of course, but Intel has the luxury of using its gate-last scheme to tune and optimize its chipmaking as it sees fit, rather than to please its customers.

Semiconductor foundry TSMC, however, is a direct GlobalFoundries competitor. But Bartlett is confident: "Our 28 nanometer solution offers significant ... advantages over the gate-last that is available in the marketplace. First and foremost, [there is ] a 10 to 20 per cent die-scaling advantage and the consequent cost advantage that comes with that, as well as still addressing the performance and power-scaling that is desired."

And GlobalFoundries' 28nm, gate-first technology is coming soon, Bartlett said. "Risk production [will begin] in the fourth quarter of this year on the first version of the 28 nanometer." In addition: "We do anticipate, as a consequence of industry analysts, that this will be a leadership technology, not just from a performance and die-scaling advantage, but also [in terms] of global capacity across the JDA ecosystem."

Bartlett also touched on the next step after 28nm: "And our 20 nanometer is well underway. It is a full-node shrink, and we do have test chips running in our Fab 1 in Dresden today. We are deeply engaged with early-adopter customers and have design kits available."

It remains to be seen whether GlobalFoundries' approach can carve a significant chunk of business away from TSMC and other semiconductor foundries. But if Bartlett's financial arguments can be matched by process reliability and on-time production, the AMD spinoff may have — wait for it — a "fab" future. ®

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