IBM preps z11 'system of systems' mainframe
Zooner zan zometime in ze zecond half
The word is on the street that Big Blue is looking to get its next-generation System z11 mainframes out the door a little sooner in the third quarter than many people might be expecting. No surprises there, with IBM's mainframe business slackening off and the prospects of selling customers System z10 boxes at anything close to a normal price being zilch, zero, zed.
The details around the timing of the launch and the exact configuration of the machines is a bit fuzzy, but the rumors are that IBM is preparing to do the launch this month, a very nontraditional time for the company to do a server launch, given the summer holidays. No announcement date is set in stone, but sources familiar with IBM plans tell El Reg that it will likely happen next week, after IBM announces its second quarter financial results and is out of its quiet period, and the chatter is that it will be on July 22.
As we previously reported back in May, the System zNext box, which is what the other placeholder name for the future mainframe is in addition to the z11 moniker, was expected to have higher clock speeds than the existing z10 engines, which made their debut in a 64-way system in March 2008.
IBM didn't talk much about that, but did say that the z11 would be "a system of systems," with mainframe system boards as well as Power7 and x64 blade servers all managed from the z/OS point of view and under the same metal skin. It will be interesting to see how IBM plugs these Power and x64 blades into the mainframe processing complex, but my guess is that it will use InfiniBand ports to link the different machines together – although it may call them something else as it does in the Power Systems lineup for Remote I/O chassis for peripheral cards and storage linked to the complex from outside the main server chassis.
So what will a System z11 look like? The System z10 is a good starting point to figure that out, since IBM likes to make incremental change with mainframes since moving to CMOS mainframe engines in the 1990s.
The System z10 was based on a quad-core processor implemented in a 65 nanometer process running at 4.4 GHz (and which was called the z6 processor because it was the sixth generation of CMOS-based mainframe engines). Each core in the System z11 box had 64 KB instruction and 128 KB data L1 caches, plus 3 MB of L2 cache per core, and a completely rehashed instruction pipeline that would allow IBM to support faster clock speeds as it moved to new wafer-baking processes in its East Fishkill, New York foundry.
The z6 cores included data compression and cryptographic units as well as decimal math units (for doing money math without having to round single-precision calculations). The z6 chip had 894 CISC mainframe instructions (668 of them implemented in hardware, the rest in firmware working in conjunction with the chip), and a single core running at 4.4 GHz was rated at 920 MIPS, yielding around 30,000 usable MIPS for z/OS workloads.
The previous System z9 (from 2005) and z10 machines (from 2008) were symmetric multiprocessing machines based on four system boards, which IBM calls processor books in the System z line; processor books are also used in the high-end of the Power Systems line. The System z10 box had 20 raw processors on the board (that's five physical z6 processors) in the 64-way variant, which had the model number 2097-E64, while smaller z10 machines had only 17 raw processors.
The raw processors could be used as central processors (or CPs) to host z/OS or other mainframe operating systems, with a maximum of 64 CPs dedicated to either z/OS or Linux. The cores in the z10 machine could also be used as zIIP or zAAP co-processors for accelerating DB2 database or Java processing (and having a much lower price than standard mainframe engines), coupling facilities for running IBM's Parallel Sysplex mainframe clustering software, System Assist Processors for supporting I/O, or hot spares.
The design with the System z11 boxes will be very similar. The shrink to 45 nanometer processes is going to allow IBM to crank up the clock speed on the z11 engines to 5.2 GHz, and according to various rumors, IBM will be doubling up that L2 cache memory to 6 MB. (IBM may even be using the embedded DRAM that debuted with the Power7 processors earlier this year, and if so, the cache could be a lot larger and yield a lot larger performance boost as it did with the eight-core Power7s relative to the dual-core Power6s in IBM's Power Systems lineup).
Sources tell El Reg that the System z11 design will keep the four-book design, but boost the number of sockets from five to six per book. The z11 engine will stay at four cores as well. That means the top-end System z11 machine will have 96 processing units, and it looks like a maximum of 80 of them will be usable by z/OS or Linux.
With the extra clock speed, larger cache, and higher engine count, plus whatever other tricks IBM has (including more than 100 new CISC instructions to speed up mainframe code), people are talking about a 60 per cent bump in aggregate processing capacity for the biggest System z11 machine, something close to 50,000 MIPS in a single system image. About 20 per cent of that comes from clock speed alone, another 25 per cent from moving from 64 to 80 cores for z/OS or Linux workloads.
It will be interesting to see if IBM even bothers to put zIIP and zAAP co-processors on the System z11 mainframes. With Neon Software selling zPrime tools to move z/OS workloads over to zIIPs and zAAPs, perhaps to best way to foil zPrime is to stop giving customers an incentive to want to move workloads to zIIPs and zAAPs. Maybe the additional blade servers in the System z11 hypersystem will be able to do some of this co-processing. But that would take a lot of rejiggering of IBM's mainframe software and very likely customer applications too. So that doesn't seem likely.
IBM could just lower the price of z11 engines to the same level it is charging for zIIPs and zAAPs, which are roughly one quarter the price of regular engines in the z9 and z10 lines. (I know, that sounds ridiculous when you say it out loud. But stranger things have happened, like Oracle buying Sun Microsystems). The odds favor Big Blue pretending that zPrime doesn't exist and that everything is hunky dory in mainframe land and charging as much money for the z11s as it can get away with. Which is still a lot less than it was charging for z10s, this being the computer business and this being 2010, not 2008. ®
It is not the Cache
"The world still runs on mainframes and its unique cache architecture which provides the highest transaction throughput of any architecture."
I guess you meant the I/O subsystem and it's IO processors ? POWER would blow the zProcessor out of the water, as much as it does with x86 and everybody else. IBM does not publicize SPECmarks for zProcessor, instead they use their "MIPS" benchmark. Guess why...
(I did some Integer benchmarking in 1999 on a cheap PC and a current S/390 CPU at that time; the results were more or less the same. I don't think this has changed)
DEC had an emulator/translator running x86 code on DEC Alpha at nearly native x86 speed (of the fastest Pentium at that time). IIRC it was called FX!32. I can't see a reason this should not be possible with the S/390 ISA and POWER.
There's actually an acronym for this kind of "complex instruction decoding on RISC microcode cores": CRISP.
-- [C]omplex [R]educed [I]nstruction [S]et [P]rocessor
Mine's the one with my Microprocessor Design and Engineering cheat sheet in the pocket.
No, it is other way around
x86 is CISC instruction set which is - in all new models of Intel and AMD processors - bolted on top of RISC core. Hardware is RISC, but decoders convert every instruction and make software see it as an classic x86.
That is one reason why x86 is so crappy and power inefficient, and why Intel's (Xeon, not Itanium) and AMD's R&D costs are higher than IBM's (at least POWER part) and Fujitsu/Sun SPARCs. That in fact let them to hang on this long against ubiquitous x86 which offsets scrappy architecture by leveraging high volume and advanced manufacturing process of Intel fabs.