AMD draws x64 battle lines with 'Magny-Cours'

Opteron 6100s lock and load

Magny-Cours, clothed

AMD did not provide a picture of the naked Magny-Cours chips snuggling up to each other, but here's what it looks like from the outside:

Opteron 6100 Package

The Opteron 6100 package: two chips making the CPU with two backs

Intel will probably make a little fun of AMD in that it can't get a dozen cores onto a single piece of silicon and had to double up. But then again, no one else, including Intel, can get more than eight cores into a single package at this point.

Jamming two chips into one package and clocking them down to get more threads to chew on software is a trick that Intel, Hewlett-Packard, and IBM have all done to move their server lineups along, and if Oracle caught a clue, it would figure out how to get multiple "Rainbow Falls" Sparc T3 chips into a single package and jack up the performance of its own Sparc machines. Oracle could drop the clock speed from the expected 1.67 GHz to maybe 1.2 GHz but double up the cores from 16 to 32 per package and maybe boost the performance of the product line by another 50 per cent or so in its four-socket Sparc T5000 series machines.

The Lisbon chips, and therefore the Magny-Cours chips, have 64 KB of L1 data and 64 KB of L1 instruction cache per core, plus 512 KB of L2 cache per core. The Lisbon chip has 6 MB of L3 cache per processor, and therefore, the double-stuffed Magny-Cours have 12 MB of L3 cache per socket. The Lisbons have six cores, but in some cases, AMD is selling partial duds (as all chip makers do) with only four working cores. So the Magny-Cours therefore come with either eight or twelve cores activated. Here's the Opteron 6100 lineup:

Opteron 6100 Table

The AMD "Magny-Cores" Opteron 6100 processors

One thing you will notice. The Opteron 6100s come in standard, Special Edition, and Highly Efficient versions, as AMD has promised a number of times (see here for instance). But the bar has moved, again as it has in the past, for that standard, SE, and HE parts means. With the four-core and six-core predecessors to the Lisbon and Magny-Cours Opterons, the standard thermal envelope parts were rated at 75 watts using AMD's Average CPU Power or ACP test. The SE chips have slightly higher clock speeds and burned 95 watts while the HE versions slow down the clocks and drop the voltage to get down to 55 watts.

(The Extremely Efficient, or EE, Opteron parts were rated at 40 watts, but these are not going to be available in the Opteron 6100 packaging, and there will be no SE parts with the Opteron 4100s but there will be standard, HE, and EE parts).

With the Opteron 6100, the SE part is running at 105 watts, the standard part is running at 80 watts, and the HE part is rated at 65 watts. So there has been, once again, some watt creepage in these definitions, as there was in the jump from dual-core to quad-core Opterons.

Intel was talking up the fact that it had embedded cryptographic instructions in the new Xeon 5600s to implement the Advanced Encryption Standard (AES) algorithm for encrypting and decrypting data. Opterons will not get similar instructions until next year, with the "Bulldozer" cores.

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