AMD did not provide a picture of the naked Magny-Cours chips snuggling up to each other, but here's what it looks like from the outside:
The Opteron 6100 package: two chips making the CPU with two backs
Intel will probably make a little fun of AMD in that it can't get a dozen cores onto a single piece of silicon and had to double up. But then again, no one else, including Intel, can get more than eight cores into a single package at this point.
Jamming two chips into one package and clocking them down to get more threads to chew on software is a trick that Intel, Hewlett-Packard, and IBM have all done to move their server lineups along, and if Oracle caught a clue, it would figure out how to get multiple "Rainbow Falls" Sparc T3 chips into a single package and jack up the performance of its own Sparc machines. Oracle could drop the clock speed from the expected 1.67 GHz to maybe 1.2 GHz but double up the cores from 16 to 32 per package and maybe boost the performance of the product line by another 50 per cent or so in its four-socket Sparc T5000 series machines.
The Lisbon chips, and therefore the Magny-Cours chips, have 64 KB of L1 data and 64 KB of L1 instruction cache per core, plus 512 KB of L2 cache per core. The Lisbon chip has 6 MB of L3 cache per processor, and therefore, the double-stuffed Magny-Cours have 12 MB of L3 cache per socket. The Lisbons have six cores, but in some cases, AMD is selling partial duds (as all chip makers do) with only four working cores. So the Magny-Cours therefore come with either eight or twelve cores activated. Here's the Opteron 6100 lineup:
The AMD "Magny-Cores" Opteron 6100 processors
One thing you will notice. The Opteron 6100s come in standard, Special Edition, and Highly Efficient versions, as AMD has promised a number of times (see here for instance). But the bar has moved, again as it has in the past, for that standard, SE, and HE parts means. With the four-core and six-core predecessors to the Lisbon and Magny-Cours Opterons, the standard thermal envelope parts were rated at 75 watts using AMD's Average CPU Power or ACP test. The SE chips have slightly higher clock speeds and burned 95 watts while the HE versions slow down the clocks and drop the voltage to get down to 55 watts.
(The Extremely Efficient, or EE, Opteron parts were rated at 40 watts, but these are not going to be available in the Opteron 6100 packaging, and there will be no SE parts with the Opteron 4100s but there will be standard, HE, and EE parts).
With the Opteron 6100, the SE part is running at 105 watts, the standard part is running at 80 watts, and the HE part is rated at 65 watts. So there has been, once again, some watt creepage in these definitions, as there was in the jump from dual-core to quad-core Opterons.
Intel was talking up the fact that it had embedded cryptographic instructions in the new Xeon 5600s to implement the Advanced Encryption Standard (AES) algorithm for encrypting and decrypting data. Opterons will not get similar instructions until next year, with the "Bulldozer" cores.
Next page: HyperTransported
Looks good, actually.
If you look at SPEC Int, a 6172 (not top bin) against an X5680 (top bin) looks like this:
Power: 80W ACP
Power: 130W TDP
ACP and TDP are not direct comparisons. In the SPEC Power benchmark, at the wall at full utilization, a 95W TDP Intel X5570 was drawing more power than an 80W ACP AMD Opteron 6174. So I have to assume that the 130W TDP is over the 95W TDP.
For floating point, the performance delta was ~20% higher for AMD. This particular comparison, however, does not show the full performance, we went with a lower bin to show the value that customers will get. People are more concerned with the power and price than raw performance. This is borne out by the fact that only ~3-5% of the market buys top bin processors. 95-97% are looking for price/performance or perforance/watt.
MCM was OK, implementation was not.
We never said MCM was bad, we said "unconnected MCM" was bad. That creates off-package traffic that should stay on package between the two dies. Somehow the press mainly picked up "MCM is bad" and the rest of the story wasn't told.
Intel proved us right by dropping that design.
Now, the bigger questions is while all of that was happening, Paul Otellini was backing the strategy as a good idea, claiming better yield and manufacturability (2 claims that we acknowledged.) So, are they going to back down from that now?
Rule of thumb
A rule of thumb that I use is the "2.5" rule - "double the specs to get a 50% improvement". YMMV