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IBM gives birth to 'wire-speed' processor

Neither server fish nor network fowl

Next gen security for virtualised datacentres

ISSCC IBM has introduced a new chip design that sits somewhere between a network processor and server processor.

Dubbed the Wire-Speed Power Processor, the chip is aimed at what IBM calls "new, evolving markets in the system industry." Applications include edge-of-network processing, intelligent I/O for servers and network attached appliances, distributed computing, and network streaming.

"I think this product is one of the most complex chips we've ever done in the history of IBM," said IBM's chief wire-speed architect Charlie Johnson while presenting his paper on the chip at the International Solid-State Circuits Conference (ISSCC) Monday in San Francisco.

The paper describes wire-speed processors as being "not network endpoints that consume data, but inline processors that filter or modify data and send it on."

"If you look into a typical tiered data center," said Johnson, "what you'll find is there's a range of systems in there, ranging all the way from the network to the file servers and database servers. And so wire-speed processing is at the convergence of network processing and database-server kinds of server processing."

IBM's new processor, said Johnson, is "sort of a blurring of the two different worlds." A wire-speed processor, he explained, is neither a network processor nor a server processor, but has attributes of both.

To that end, the first-generation IBM wire-speed processor described by Johnson not only includes 16 quad-threaded cores, but also a battery of task-specific, multi-engine accelerators to handle crypto, XML, compression, and RegX duties, along with four 10 gigabit-per-second Ethernet and two PCIe Generation 2 channels.

The processor's A2 cores are small, 64-bit PowerPC cores based on IBM's embedded architecture - "a little bit different from our server architecture," said Johnson. Full vitualization and hypervisor support is also included, along with some new instructions that allow for low-latency interaction with the processors' accelerators.

The chip's 16 cores run at 2.3GHz, although Johnson pointed out that they can be run up to 3GHz, but "the power-performance efficiency isn't as good up there, so that's not really interesting to us." The accelerators and I/O channels run at a variety of speeds, with some of the accelerators able to match the cores' clock speeds.

The chip is built using 45nm SOI technology, contains 1.43 billion transistors on its 428mm2 die, and depending upon how many cores are active will consume between 20 and 65 watts, with typical usage being in the 55W range.

But don't expect to plop a device with one of these processors into your data center next week. IBM's Wire-Speed Power Processor is still in the developmental phase. When showing a photo of the chip die at the end of his presentation, Johnson said: "I just pulled this one out of the fab on Thursday." ®

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