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Intel 'Tukwila' born after long and painful labor

Blame it on marketing

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Intel officially unveiled its long-delayed Tukwila "mission-critical" server processor today - now dubbed the Itanium 9300 series - providing a few more details about the 2-billion transistor part and giving some color on why it was over three years late.

Made in conjunction with this week's International Solid-State Circuits Conference (ISSCC) in San Francisco, the announcement was not unexpected, as we reported earlier.

"Simply put, this is a technology marvel," enthused Kirk Skaugen, Intel vice president of the Intel architecture group and general manager of the data center group, focusing on what he referred to as the Itanium 9300's "mission-critical innovation."

The 9300 is Intel's seventh generation of Itanium, and the company has committed to, as Skaugen put it, "at least two generations more," code-named Poulson and Kittson. Describing the fact that all three Itaniums will be both socket and binary compatible, he said: "There's one thing that people really demand here, and that's the ability to not have to do 'forklift upgrades' on a regular basis. They want investment protection."

Skaugen also noted that the multithreaded four-core 9300 is the first Itanium that will allow eight processors to be connected gluelessly, without a node controller, in the same system. He also mentioned that HP will offer 64-socket 9300 systems with node controllers.

Like Intel's latest x86 processors, the 9300 will take advantage of the company's TurboBoost technology, which bumps up the performance on individual cores when other cores are idle due to such factors as inefficiently parallelized applications.

That boost, however, is far from spectacular. Responding to a question about its effect on the Itanium 9350, Skaugen noted that: "The top frequency is 1.73GHz, and will boost to 1.86GHz."

Skaugen also pointed out that the 9300 is the first Itanium to use the QuickPath Interconnect (QPI), which he claims offers nine-times the performance of the now-obsolete frontside bus with the help of a latency-reducing snooping protocol called Directory Snoop.

"We spent a tremendous amount of time on the memory subsystem," said Skaugen, citing "architectural decisions that were made by marketing." And this course-correction in the 9300's development was one of the prime causes for the delay in Tukwila's birthing as the Itanium 9300 series. "As many of you know," he said, "about a year ago we made a change, where we moved away from fully buffered DIMM memory to industry-standard DDR3 memory."

Skaugen claimed that it wasn't the fault of Tukwila's central design principles that the 9300 series was late. "It hasn't necessarily been the issue that Tukwila wasn't functional, it was the fact that we changed a pretty major part of the design - that entire memory buffer chip didn't exist a year ago."

Despite the delay that it caused in Tukwila's development, Skaugen argues that dropping FB-DIMMs was worth the delay. "We think that DDR3 memory, which is obviously mainstream across all of our Intel Xeon 5500 products today is a good architecture as we look forward, and provide this investment protection from Tukwill - today 9300 - to Poulson to Kittson."

The change, according to Skaugen, was "to make sure we could deliver a long roadmap - six, seven, eight years kind of thing - on this next-generation [HP] Superdome and other platforms from our OEMs."

The change to DDR3 also allowed the 9300's platform to share major platform components with the Nehalem EX Xeon processors, which Skaugen said would appear in the next 90 days. "Many, many years ago," Skaugen reminisced, "at the Intel Developer Forum, we promised something called the Common Platform between the Xeon architecture and the Itanium architecture."

"A lot of people, I don't think, thought were were serious when we talked about this five years ago," Skaugen joked. Then he ticked off the common platform elements that will be shared by the two processors: the I/O hub - which can scale to 72 PCI-Express lanes; the ICH-10 controller hub; the system-memory interconnect; and the 7500 memory-buffer.

"Why do we care about this memory buffer?" Skaugen asked rhetorically. Then he answered himself: "Well, the combination of the memory controller and the memory buffer enables us to do those reliability features...but it also allows us with 16GB DIMMs to scale up to a terabyte of memory."

The common elements will also enable OEMs to build node controllers common to Xeon and Itanium systems. "What's important is the R&D economics," Skaugen said. "If you're building a large-class Itanium system, the R&D reuse that you can get onto a node controller now over to your Xeon-class system is very, very strong."

And that R&D reuse is intended to remain reuseable through Poulson and Kittson. Although he declined to give any details on Kittson, Skaugen said: "We going to double the performance - or more - again with Poulson, just like we did with Tukwila, and we're going to have significant architectural advancements...

"It has instruction-level enhancements, it'll be socket compatible, it'll be binary compatible so you don't have to change anything in your software, it'll have more cores, enhanced hyperthreading, etcetera. And we'll be moving to 32-nanometer technology."

But don't expect Poulson and Kittson to show up at the same "tick-tock" yearly time frame as do Intel's x86 chips. "We're going with two-year, approximately, beat rate."

With Tukwila the Itanium 9300 series being released so far behind schedule, Skaugen took pains to assure his audience that Poulson won't meet the same fate. "What we've done is now we've actually built a completely seamless and single tools suite...which greatly enhances the predictability.

"We have hundreds and hundreds of engineers working on Poulson and Kittson right now...We're on an approximately every two-year beat rate for this processor, so that's what we're staffed to go do."

We'll check back in 2012 and see if those hundreds and hundreds of folks make the Itanium's next deadline. ®

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