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European Commission pays IDC to take a hard look at HPC

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The European Commission has commissioned IT market researchers and analysts at IDC to work with some of the top European supercomputing labs to rationalize and coordinate the efforts to push into petascale and exascale computing within Europe.

HPC experts from Teratec, in France, Daresbury Laboratory, in the United Kingdom, Leibniz-Rechenzentrum and Forschungszentrum Jülich, in Germany (that's two different labs), will be working with the supercomputing experts at IDC to come up with a "strategic agenda" for HPC projects in Europe.

One of the goals of the study is to advance what the European Union calls "open science" within the member countries, which basically means collaboration among scientists and the computing facilities that are increasingly needed for them to perform basic research. European politicians are also keen on keeping pace with the United States, Japan, and China in the flops arms race, and are also keen on investigating options for local sourcing of HPC systems.

The number of HPC suppliers (and I don't mean resellers) has dwindled in the past decade, and European players are pretty thin on the ground, unless you want to consider IBM and Fujitsu as locals. [IDC is of course based in England - New England that is]

"The link has been firmly established between HPC and scientific and economic advancement," explained Steve Conway, research vice president in IDC's technical computing group, in a statement announcing the seven-month consulting gig with the EU. "The investments needed for the next generation of HPC systems will be substantial. Deciding on the optimal areas of investment - systems, storage, software, and people skills - that are most valuable to European HPC users, and the wider economy, is critical to the EU's success in developing its HPC agenda. Many countries are installing multiple petascale supercomputers today and are laying the foundation for using exascale systems in a few years."

Under the contract, IDC and the experts at the above-mentioned HPC labs will be doing a comparative study of supercomputing investments on a global basis from 2010 through 2020, the various architectures HPC centers are expected to deploy, and the impact that HPC has on scientific and industrial research.

If the EU wanted to shake things up a bit, it would establish a company explicitly to develop massively parallel supercomputers based on the ARM RISC processor running SUSE or Ubuntu Linux. The ARM chips have some pretty serious price/performance advantages and have floating point and media processing units that could be put to good use. The chips could be fabbed at the GlobalFoundries wafer bakers in Dresden, Germany to keep it local, and Fujitsu could be commissioned to build system boards and clusters.

This is, more or less, how IBM's BlueGene and Cray's Red Storm (XT4 and XT5) parallel supers sprung into being. Without hundreds of millions of dollars of support from Uncle Sam, these experimental systems would have never come to market, much less been commercialized and sold to non-government super labs. You could argue that the US government is underwriting a lot of the cost of developing the Power7 chips due next week, too.

The point is, supercomputing has always been much more involved with national pride than other forms of computing, and at this point, computer component design is largely done by US-based companies, even if a lot of the manufacturing and assembly is done overseas. It is foolish for the members of the European Union to lose the skills and jobs behind the engineering, building, and programming of powerful parallel computers. ®

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Latest Comments

Arm Cortex-A9 MPCore Quad

did you miss the fact the Arm Cortex-A9 MPCore™ multicore processor SoC , system-on-a-chip is and Has all these things you ask for and more already joeuro ?

http://www.arm.com/pdfs/ARMCortexA-9Processors.pdf

and due for a commercial 2 gig quad release soon enough.

its SIMD is called NEON and its 128bit wide like and on par with the PPC Altivec SIMD

but more upto date and faster op codes etc.

its not clear if the linux Arm Cortex branch librarys are in any way optimised and made to take advantage of the SIMD, like apple OS librrys did for PPC SIMD altivec yet?

has anyone checked the Linux ARM Cortex codebase to see if its got these libray SIMD optimisations !, it might be intersting to know, and see any benches for this on Cortex SoC.

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H.264 HighProfile@L4.1 Arm

OC the A9 would be so much nicer if they bolted this on to it as a core genric item alongside the 2gig quad SIMD

http://www.imgtec.com/news/Release/index.asp?NewsID=440

"...Both VXE320 and VXE360 support H.264 High Profile encoding, offering improved video quality at lower bitrates. Features such as B-frames and CABAC encoding enable the consumer to record and transmit video at the highest possible quality, whilst maintaining the low data rates essential for storage and network transmissions. The provision of High Profile allows devices using POWERVR VXE360 to typically offer up to a 10x improvement in recording capacity of HD video compared to today's devices which use the less efficient M-JPEG algorithm.

The cores are scalable, allowing Full HD video to be encoded, as well as offering the ability to record at extremely high frame rates, (e.g. >1200 fps at QVGA), for detailed slow motion capture – one of the "hot new features" seen at the recent CES consumer electronics show in Las Vegas.

....

The VXE320 and VXE360 cores' multi-standard support has been tested with a wide range of raw image data to ensure high compression ratios with excellent visual quality and minimal image degradation. Supported standards include: H.264 HP@L4.1; MPEG-4 SP@L5.0; H.263 P0@L50; M-JPEG Baseline Profile 4:2:2 & 4:2:0; and JPEG Baseline Profile 4:2:2 & 4:2:0.

All POWERVR VXE video encoders contain a powerful real time stream manager, based on Imagination's META MTX 32-bit embedded processor, which performs rate control as well as overall core management functions. The VXE cores' comprehensive and flexible rate control algorithms include constant, variable, constant QP and low delay bit rate control to match the requirements of the end application. The unique architecture of POWEVR VXE enables future rate control requirements to be met using existing hardware, without the need for new silicon.

...."

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no stinkin locked down IPad.

and if jtag'ed mobile phones bug you so much joeuro then just go order some generic Arm A8 efika-mx-smartbook or some Efika MX A8 Open Client motherboards

http://bbrv.blogspot.com/2010/02/efika-mx-smartbook.html

for something Arm Neon SIMD based to play around with, you dont need no stinkin Arm locked down IPad.

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