Intel uncloaked a few more details on Wednesday about its line of consumer-level 32nm Westmere processors, which were previewed late last year and formally announced at last month's Consumer Electronics Show.

While most details of the Westmere consumer processors - known in marketing parlance as the Core i3/i5/i7 line - were already known, one nugget discussed today caught our interest: There's a speed boost available to the on-package HD Graphics cores in the mobile versions of the Core i3/i5/i7 parts that's similar to the Intel Turbo Boost Technology available in the Core i5 and i7 compute cores.

Dynamic Frequency's graphics goose - mobile processors only

Turbo Boost allows a chip to both boost a core's clock speed when an app needs some help and also save power by shutting down unneeded cores when an app isn't taking advantage of them. The graphics equivalent, called Dynamic Frequency, performs the same boost mojo for Westmere's integrated 45nm graphics die.

Turbo Boost is incremented in 133MHz "bins," with a maximum increase of eight bins, provided that the chip stays within its power and thermal specs. Dynamic Frequency, according to Intel, can provide the HD Graphics core with an up-to-3X frequency increase in graphics-intensive bursts.

These details were revealed in a conference call with reporters in preparation for Intel's participation in next week's International Solid-State Circuits Conference, to be held in San Francisco. An Intel rep told The Reg that the Dynamic Frequency feature had been discussed with certain product reviewers at CES, but this is the first time it has been highlighted in a company presentation.

In addition to the graphics-boosting oomph of the mobile line's Dynamic Frequency capabiliaty, Intel engineer Nasser Kurd also emphasized two of the Westmere processors' new power-saving features. First, the chips' L3 cache and queues - elements of what chip folks call a processor's "uncore" - can also be powered down when the cores are idling. Second, and unlike the previous Nehalem architecture, the chips now now include SRAM that's dedicated to saving a core's state, which removes the need for keeping the last-level cache powered up when the core is idle.

More details are certain to emerge during the ISSCC deep-geek presentations and discussions next week. ®