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ISSCC: Home cooking at the wafer bakers

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Big Blue will, as you might expect, show off its impending Power7 chip, which was highlighted at last summer's Hot Chips conference in Silicon Valley and further detailed by IBM at the SC09 supercomputing conference last November. As El Reg has reported previously, the Power7 chip is implemented in IBM's 45 nanometer SOI processes and sports eight cores (with four threads each) and 32 MB of embedded DRAM that is used as a shared L3 cache. The first Power7-based systems are expected to be announced sometime in February.

IBM's chip designers will be showing off another experimental Power7 derivative, an unnamed 2.3 GHz "wire-speed Power processor" that sports 16 cores and 64 threads. This chip will burn 50 per cent less power (compared to what, IBM doesn't say) and will dissipate 65 watts of heat running at 2 GHz at 0.85 volts. The chip includes eDRAM as the on-chip L3 cache, like the Power7 does, and this could very well be a future Power7+ chip that Big Blue is showing off. (Power4+, Power5+, and Power6+ were not particularly impressive, and IBM may be trying to demonstrate that it can tock as well as tick, to use the Intel lingo.)

Finally, Hitachi will be showing off a multicore chip implemented in 45 nanometer processes that has eight general purpose cores, four "dynamically reconfigurable processors," two 1,024-way matrix co-processors, and on chip peripherals and interfaces. Hitachi says this chip runs at 684 MHz and will deliver 37.3 billion operations per second per watt at 1.15 volts. ®

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