Tilera pushes to 100 cores with mesh processor
Super-efficient Linux engine
Upstart massively multicore chip designer Tilera has divulged the details on its upcoming third generation of Tile processors, which will sport from 16 to 100 cores on a single die.
That will give Tilera bragging rights for cramming the most general purpose computing cores onto a die, although graphics chip makers are already jamming hundreds of cores onto a die. For instance, the future Fermi graphics chips from Nvidia, which will appear in GeForce graphics cards as well as in Tesla graphics co-processors, have 512 cores on a single chip.
Intel is cooking up its own 64-core Larrabee graphics processor, which will reportedly have a single, simplified x64 core paired with a vector coprocessor and a shared, coherent memory structure that allows the L2 caches for the memories on each core to be accessible to all the other cores. Intel could be planning to ship Larrabee chips with 8, 16, 32, 48, and 64 cores, using 45 nanometer high-k metal gate processes and probably as much as 128 cores with a shrink to 32 nanometer processes.
There are a lot of differences between the Tile family of chips and these graphics processors, but the key one is that the Tile multicore processors run Linux directly (albeit a homegrown one) and are being designed not just for digital signal and networking processing, but to run that standard LAMP stack - Linux, Apache, MySQL, and PHP.
The architecture of the original Tile64 and second-generation TilePro36 and TilePro64 chips has not changed dramatically with the Tile-Gx series of chips, which are being preview today even though they will not start shipping until the end of 2010. Tilera, says Bob Doud, director of marketing, is talking about its roadmaps with its partners, and rather than have the information just leak out all over the place is telling the world what it is up to more or less at the same time. (Which it doesn't have to do, being a privately held company and all).
When Tilera came out of stealth mode in August 2007, it had a 64-core RISC-like chip in an 8x8 grid with a sophisticated mesh interconnect, now called iMesh, that links all of the cores and their L2 caches into a single, coherent system using five different mesh interconnects all liked together by a switch implemented in silicon. This chip was implemented in a 90 nanometer process from Tilera's fab partner, Taiwan Semiconductor Manufacturing Corp, and it was put on a PCI-Express card for potential customers to play with to see how they might put it in network security, video streaming, and other products.
These original Tile64 processors implemented 32-bit cores (which I strongly suspect but do not know are based on a heavily streamlined and tweaked MIPS RISC design, since Tilera has not disclosed the instruction set of the core). Each Tile64 chip could run at 700 MHz or 866 MHz, and each had 8 KB L1 data and instruction caches and 64 KB of L2 cache that was meshed together into a shared 5 MB coherent cache that functioned like an L3 cache for all the cores. The Tile64 had four DDR2 main memory controllers, two Gigabit Ethernet ports, two PCI-Express controllers, two 10 Gb/sec XAUI interfaces, and two flexible I/O ports for supporting flash or disk drives.
With the second generation of Tilera chips, the TilePros, announced last September, the L1 caches were boosted to 16 KB, the L2/L3 cache was boosted to 5.6 MB, and the company put out a 36-core variant as well as the 64-core version.
These chips also included a new feature called "hash for home," probably code-named Amsterdam, that automagically spread data in the caches across the processors so a set of cores and caches didn't end up being hot spots. Tilera also added SIMD instructions to assist with video and audio handling plus some new memory manipulation instructions. The Tile chips were also giving a memory striping feature, akin to RAID data striping on disk drives, and another feature to allow a core to have direct access to cache memory without having to go through main memory to get a snippet of data.
Even though the clock speed didn't change for the TilePro36 and TilePro64 chips, the performance boost was somewhere between 1.5 to 2.5 times with only a 5 per cent increase in power consumption. And this was all accomplished by staying at the 90 nanometer processes, which are basically dirt cheap. The TilePro64 consumed 19 to 23 watts running real workloads, and the TilePro36, which only clocked at 500 MHz and which had only 3.2 MB of L2/L3 cache, ranged at 10 to 16 watts under load.
Sponsored: DevOps and continuous delivery