Rambus threads DDR3 memory

Weaves a solution for multi-core hosts

By Chris Mellor, 21st September 2009

Rambus has devised a way of making DDR3 memory multi-threaded, so that it can better support multi-core servers.

It has worked with Kingston Technology to build a threaded module prototype using DDR3 DRAM technology. The two say early results show an improvement in data throughput of "up to 50 per cent, while reducing power consumption by 20 per cent compared to conventional modules".

They reckon that slow memory transfers will hold up the increasingly pervasive multi-core servers and PCs, because the CP engine can handle more data than memory can deliver. Rambus thinks "multi-core computing requires more bandwidth and higher rates of random access from DRAM memory."

The way to do this with DDR3 is to parallelise it. Threaded memory module technology - implemented with industry-standard DDR3 devices and a conventional module infrastructure - partitions modules into multiple independent channels that share a common command/address port.

The modules "support 64-byte memory transfers at full bus utilisation, resulting in efficiency gains of up to 50 per cent when compared to current DDR3 memory modules. In addition, DRAMs in threaded modules are activated half as often as in conventional modules, resulting in a 20 per cent reduction in overall module power."

Rambus will showcase a static demonstration of this prototype at the Intel Developer Forum, September 22 – 24, 2009 at Moscone West in San Francisco, where a Rambus staffer will give a talk on the topic. ®

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