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AMD Bulldozer core to weave multiple threads

But not the way Intel's HyperThreading does so

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AMD's 'Bulldozer' core design will incorporate some kind of simultaneous multithreading (SMT) technology, it has emerged. But it's not going to be like Intel's HyperThreading the smaller chip maker has insisted.

This week, AMD showed off its 'Magny Cours' chip architecture, a design that crams in six of the cores found on its 'Istanbul' chips, each with 512KB of their own L2 cache and 6MB of shared L3 cache.

An architecture roadmap revealed at the Hot Chips conference shows the 45nm processor - out next year in its initial form - will soon evolve into a 12-core beast with 12MB of L3. It'll gain a four-channel 1333MHz DDR 3 controller along the way - Istanbul has a two-channel controller the peaks at 1066MHz DDR 2.

It's not clear whether the 12-core Magny Cours will use the Bulldozer core from the word go, or get it in a subsequent revision.

Either way, Bulldozer itself will deliver the ability to handle multiple threads simultaneously, EE Times reports after a chat with Pat Conway, principal member of technical staff at AMD.

He didn't say much more - and AMD has subsequently stated for the record that it has made no formal announcement on adding SMT to Bulldozer - though he did indicate AMD's approach will operate "in a different fashion than HyperThreading".

HT allows a second thread access to core resources that have not been called upon by the first thread. That's not always possible, which is why HT delivers a performance boost generally well below that of adding a further physical core: improvements of 15-30 per cent and up to 80 per cent, respectively.

Intel's approach isn't the only one, and SMT is implemented in a number of different ways in MIPS, IBM Power and Sun Sparc processors. ®

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