Intel has fixed the BIOS password bug in its new 34nm NAND chips and has also introduced 3-bits per cell 34nm process chips.

The bug affected users of Intel's X25-M and X18M 34nm process NAND chips. If they set and then amended a BIOS password in any way, the data on the chip became unavailable. A downloadable firmware fix, available here, solves that embarrassing problem.

The X25-M and X18-M are 2-bit per cell multi-level cell (MLC) flash solid state drives. Intel and Micron, who have a flash foundry partnership, Intel Micron Flash Technologies, have now developed a 3-bit MLC chip at the 34nm process level. This increases the storage capacity of chips. A 3-bit X25-M, if one were made, would hold half as much data again as the 2-bit X25-M. Adding a third bit also lowers the cost per flash bit.

However it lowers reliability as well, and the Intel/Micron 3-bit MLC reliability is not good enough, yet, for anything other than flash thumb drives. Micron is sampling 3-bit MLC chips for such use.

SanDisk and Toshiba announced a 4-bit MLC NAND technology in February this year, saying it was built using a 43nm process. There is a race going on to develop the highest-density flash with sufficient reliability and speed for deployment in thumb drives and, with increasing reliability needed, mobile Internet devices, smart phones, netbook and notebook storage and enterprise storage and server caching applications.

Jim Handy of Objective Analysis thinks that SanDisk's most recent teleconference indicates that SanDisk and Toshiba will have a 32nm 3-bit chip, which is expected to begin to ship at the end of the year. He says Micron and Intel: "have plans to move to the next process, one they call their "2xnm generation" (20-29nm) by the end of the year. They are confident that their 3-bit technology is capable of being used at this process geometry."

Handy also said: "By the first part of 2010, manufacturers with 3-bit 3xnm product will be impressively more profitable than their competition." ®