Toshiba hopes for 3D flash chip within three years
Very small drill needed for 16 layer hole
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Toshiba has developed a 3-dimensional NAND flash chip using 2 bit multi-level cell technology.
The basic idea is to stack layers of flash memory atop one another to build a higher capacity chip more cheaply than by integrating the same number of cells into a single layer chip. The stacked chip would also occupy a smaller area than a single layer chip with the same capacity.
Matrix Semiconductor was working with this technology in 2001. SanDisk bought Matrix in 2005. Toshiba commenced its own 3D memory developments in 2007. SanDisk and Toshiba, who have joint NAND manufacturing operations, got together in 2008 to jointly develop 3D memory further and this development is still ongoing.
Tech On reports that Toshiba calls its 3D implementation P-BiCS (Pipe-shaped Bit Cost Scalable) and has a 16-layer, 32Gbit prototype chip, built using 60nm process technology. The chip's area is 10.11 x 15.52mm, and the actual NAND cells are smaller than those to be found in the 32nm process technology flash chips coming from Toshiba this year.
One problem area has been the construction of holes through the layers. In a previous implementation an insulating film on the walls of this hole was damaged during the manufacturing process. Toshiba has reduced the tunnel wall insulation damage by making the insulating film from Silicon Nitride (SiN) rather than Silicon Dioxide (SiO2).
Currently the hole can be created through eight layers. The 16-layer prototype is in fact two stacked 8-layer units. Hideaki Aochi, the chief specialist in Toshiba's Advanced Memory Device Technology Department, said: "One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost." That might involve creating a 16-layer hole.
In the previous chip, cells were connected in a linear fashion. The new chip has a U-shaped cell string to enable the multi-level cell (MLC) operation. Certain logic operations have also been moved in the new implementation from the lower part of the cell string to the upper part.
Jim Handy of Objective Analysis, confirmed the area advantage of this 3D prototype: "If you used a 66nm process to make a standard MLC NAND it would have a die size almost four times as large at 600sq mm vs the 156sq mm of the Toshiba chip. Even with 4-bit MLC, the standard NAND part would be twice the size of Toshiba's new part."
Handy reckons Toshiba's technology is cool: "(Toshiba) understood some of the limitations of the prior chip and came up with ingeniously simple solutions to them. Making a U-shaped line improved the nitride's quality to something that could support 2-bit MLC. Moving the logic to the top from the substrate (which is far more conventional) gave them faster access since metal can now be used for the source lines rather than a diffusion layer."
He believes that production 3D memory chips could appear in three years time, as Toshiba hopes. ®
