Is Moore's Law, the driving force behind the technology and economics of the chip business, going to take a holiday? The analysts at iSuppli think so. And sooner than you think, and maybe not for the reasons you are thinking.

The old trick of cranking up clock speeds on shrinking chips to boost performance has been dead for several years now, which was the first phase of the application of Moore's Law, which was followed by integrating more and more system components onto chips. When power consumption and heat dissipation issues put the kibosh on cranking clocks, chip makers started slapping multiple cores onto chips to boost performance, and have been stuck, more or less, at the same clock speeds for the various architectures.

The clock ceiling is near 1.5 GHz for Sparc T and Itanium processors at the moment, and around 3 GHz for x64 processors. It is 3 GHz for Power5 chips and is around 5 GHz for Power6 processors, which has a different pipeline from Power5. But adding cores has its own issues, as IT industry giant David Patterson of the University of California at Berkeley explained last fall at the SC08 supercomputing trade show, and analysts at Gartner talked about earlier this year.

Basically, just because chip makers can keep adding cores, it doesn't mean that the application software and the end user workloads that run on this iron will be able to take advantage of these cores (and their varied counts of processor threads) because of the difficulty of parallelising software.

iSuppli is not talking about these problems, at least not today. But what the analysts at the chip watcher are pondering is the cost of each successive chip-making technology and the desire of chip makers not to go broke just to prove Moore's Law right.

"The usable limit for semiconductor process technology will be reached when chip process geometries shrink to be smaller than 20 nanometers (nm), to 18nm nodes," explains Len Jelinek, director and chief analyst for semiconductor manufacturing at iSuppli in a new report.

"At those nodes, the industry will start getting to the point where semiconductor manufacturing tools are too expensive to depreciate with volume production, i.e., their costs will be so high, that the value of their lifetime productivity can never justify it," he adds.

At that point, says Jelinek, Moore's Law becomes academic, and chip makers are going to extend the time they keep their process technologies in the field so they can recoup their substantial investments in process research and semiconductor manufacturing equipment. Look at these pretty money curves going all flat:

As you can see from the chart, iSuppli reckons that the ramp up to 90 nanometer (0.090 micron) technology by chip makers was steep, and then fell off just as quickly. (This is not chip count or aggregate transistor count produced, but the revenue derived from chips using each process.) And while the ramp to 65 nanometer processes was just as steep, it is not going to peak the same way and iSuppli reckons that 65 nanometer processes will be used to make chips at a more or less steady state heading out to 2012.

Look at the 45 nanometer ramp. It is not as steep as the 90 nanometer or 65 nanometer ramps, and rather than peaking, it heads up very slowly in a straight-line fashion to just rise above the 65 nanometer peak.

It took about a year for 65 nanometer to hit its peak (from the breakeven point where it was generating no revenue in early 2007), but 45 nanometer processes, which started making money in early 2008, are going to take until late 2011 or early 2012 to hit the same peak as 65 nanometer hit. Four years instead of one.

"The semiconductor industry will be living with historical generations of technology longer than it did before," Jelinek says. "You are not seeing these geometries rise and fall off the way they did before. Rather, they are living on."

And they are living on because chip makers are going to be forced by the high cost of each generation of chip technology to maximize for money generated by a process instead of chip performance and lowering the cost of chips. "Historically, the focus in the semiconductor industry was always how quickly you could move to the next geometry node. Now the question is how to make money by sustaining a specific node."

One way that iSuppli reckons that chip makers will extend the life of future chip processes is to go three dimensional in chip designs. Instead of trying to shrink geometries, chip makers will take the system-on-chip and multicore architectures to a new extreme.

But this still won't solve the software parallelism problem that is looming large. While this is not directly the chip makers' problem, if that problem doesn't get solved, it won't matter how much stuff chip makers can cram into a chip. No one buys a computer that doesn't offer more performance or more features, and if the software can't give an end user a better experience, they don't buy the computer and the chip is a dud, no matter how cool it might be technologically. ®