Rambus pitches XDR2 for future memory
You know you want it
Hot on the heels of the US Federal Trade Commission's decision two weeks ago to drop a seven-year antitrust lawsuit against Rambus, the memory chip designer is pitching its bag of technology tricks, collectively known as XDR2, as the future of main memory and graphics memory for PCs and servers.
If you are a cynic, you might be thinking that all the talk today about the technologies that Rambus is rolling into XDR2 main memory - you can read a detailed white paper outlining the whole XDR2 enchilada here - is really more about laying the groundwork for future lawsuits should PC and server makers and their memory suppliers decide to nick a few ideas here and there to goose DDR memory subsystems on their future machines. Count me a cynic.
Having said that, Rambus makes a pretty good case, as always, that the current memory technology is going to hit some walls - and sooner rather than later, as processors get more cores and embrace technologies such as virtualization. Both are a substantial strain on memory systems as processor utilization rates are driven higher and are therefore chewing through data at a much faster pace.
As Rambus draws the memory bandwidth over time curve, the industry is going to need to kick out something as a follow-on to DDR3 pretty soon. DDR3 memory is just now being used in production in "Nehalem EP" servers from Intel, and Core i7 PC and workstations also use DDR3 memory. But DDR3 has yet to be adopted by Advanced Micro Devices. The six-core "Istanbul" Opterons, which have yet to be launched but which the company said last month, would start shipping for revenue in May, support DDR2 main memory.
AMD doesn't get to DDR3 until the six-core "Magny-Cours" Opterons debut in the first quarter of 2010. Most RISC/Unix servers are still using DDR2 main memory as well and will gradually make the shift over to DDR3. So there is some time to worry about what is beyond that. And Rambus wants the industry to worry, just as it did back in the 1990s when it tried to use the same tactic - and Intel's own greed - to shift the industry toward Rambus memory and away from SDRAM. (It didn't work because chipset makers just balked).
Anyway, Rambus says that based on past data trends for DDR SDRAM main memory, sometime around next year or so the industry in going to need to put into production a successor to DDR3, which currently scales from 1.03 GHz to 1.6 GHz and which offers module bandwidth as high as 12.8 GB/sec. What Rambus is projecting is a need for memory speeds that range from 2.13 GHz to 3.2 GHz and that deliver twice that bandwidth (from 12.8 GB/sec to 25.6 GB/sec, depending on the speed of the memory). And still keep inside of a fairly small power envelope.
This is a big challenge, of course, because cranking up the clock on memory boosts the power draw, as does adding more memory channels to the processors to balance core counts against the memory needs for those cores. Rambus says the industry needs to expect between three and six memory channels per processor socket (up from three with the Nehalem EPs and their on-chip DDR3 memory controllers) and, more importantly, memory chip modules that burn under 7 watts when they are active and less than eight-tenths of a watt when they are idle. Backwards compatibility with DDR3 memory controllers would also be a plus.
To make its case for XDR2 technologies, Rambus shifted the conversation away from system main memory and on to the memory used in graphics cards, GDDR. How this will translate into system main memory is not clear, but the implication is that Rambus is going to try to license technology to graphics memory makers first and then try to foster a kicker to DDR3 main memory down the road.
Not one to be shy about its technical prowess, Rambus says that its original XDR memory is far superior to the basic outlines of GDDR5 graphics memory and that its proposals for technologies to be included for XDR2 will just blow GDDR5 away. (AMD has been shipping GDDR5 memory in its Radeon video cards since last year). Rambus says its XDR2 can deliver up to 12.8 GB/sec data rates, twice the peak bandwidth of GDDR5, and do so while consuming 30 per cent less power at equal bandwidth. Or, for equal power, XDR2 can provide as much as 50 per cent more bandwidth than GDDR5. The feeds and speeds comparing XDR2 to GDDR5 are in this graphic to the left.
The secret sauces in the XDR2 memory include a 16X data rate (eight times the double-data rate memory used in DDR and GDDR memory), which allows the high bandwidth at relatively low clock speeds. XDR2 memory also has a technology called micro-threading, which partitions an eight-bank DRAM core into 16 independent banks and which allows graphics cards and multi-core processors to use multiple paths to get to those virtual memory banks and thereby boost memory bandwidth. The XDR2 memory also implements other goodies, such as the fully differential memory architecture (FDMA), which implements differential signaling on the links between memory controllers and the XDR2 DRAM chips, as well as using Flexlink C/A point-to-point communications and an enhanced FlexPhase signal method.
Let's see what the memory, processor, and PC and server makers do now. Your move, guys, and you can bet that the lawyers working for Rambus are watching very, very closely. ®
"Cell and the PS3 were designed to be used in a system that had XDR memory."
I doubt the Cell was designed with that in mind. Forcing processor elements to only be allowed to access their local caches directly greatly simplifies the design of the processor. It makes a lot of sense from both power and cost perspectives.
The fact that RDRAM has such high bandwidth does make it the logical choice for Cell based systems with such a high SPU to PPC ratio, which could have been one of the guiding factors in the design of the PS3.
Of course the SPUs work that way. Cell and the PS3 were designed to be used in a system that had XDR memory.
re: FTC v. RAMBUS - But the FTC dropped their case which could only mean that RAMBUS is a pretty cool guy...
I really hope you're being Ironic, otherwise you need to have your sarcasm detector looked at! I reckon that RAMBUS only gets to pull that stunt once.
Re: Oh not you again
"I don't need data in packets of 2KB. I need it in cacheline-sized chunks."
No, you don't. You used to - back in the days when the world was grey and men walked quickly. These days, however, it is far better to design your data structures to be cache friendly and copy large amounts of data into the L2 cache, work on it there (where you will then get cache-line sized transfer to and from the L1 cache) and then copy the results back out to system memory. And, unsurprisingly, this is exactly how the SPUs on your PS3's Cell processor are designed to work. (And in fact it's the only way they work.)
Assuming the architecture will solve everything for you and stalling while you wait for the next cache line to be fetched is soooo last century. I bet you think letting threads run on any available core is still a good idea too.
Paris, because she likes large packets too.
In honor of this article
I just shutdown my rambus-based Dell Precisions... For the last time. They go to the scrapheap tommorrow. I transferred their workloads to an IBM RS/6000 and a Sun Ultra 1 - and the funny thing? Both those systems have more RAM than the Precisions did. Could it possibly be because buying RDRAM would have fucking bankrupted me? Even when compared to ridiculous crazy proprietary nutzo-RAM? Yeah, I think that's it.