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Repeating chip history

This link on the IBM Research site that puts a name to the Power6+ chip: Eric Fluhr. According to his biography, Fluhr works for Systems and Technology Group's Austin, Texas, lab; after getting a BS in computer science and MS in electrical engineering at the Georgia Institute of Technology 1996, he started working at IBM Austin on the Power3 chip in custom and array circuit design and circuit logic verification.

Late in the Power4 chip effort, according to this bio, Fluhr switched to load/store logic design, a job he did through the development of the Power5 chip and by Power6, he led the load/store physical design team. Here's the important bit: Fluhr is the microprocessor technical leader for the Power6+ chip. So we are not hallucinating.

In the i world, Power6+ is starting to pop up in PTFs (short for Program Temporary Fix, IBM lingo for a software patch) for the i 6.1 operating system as well, as in here and there. (I don't claim this is an exhaustive list, mind you. This is what I could find.) And on the p side of the house, here's a reference that talks about various processor compatibility modes that are necessary to support Partition Mobility, an AIX feature that allows for a logical partition to be live migrated from one physical System p or Power System box to another one.

What no one seems to know is what the Power6+ chip will be. A radical design change seems unlikely - that's not the way IBM does things. And it doesn't look like IBM will do a chip manufacturing process shrink from the current 65 nanometer processes to 45 nanometers, although you would think it would want to test out the 45 nanometer processes before Power7 puts them in production. The roadmap above from 2005 suggests that Power6+ would come with "enhanced transistor for higher frequencies," something that was removed from the late 2006 roadmap which nonetheless suggested that Power6+ would be a "high freq multi-core" chip.

That suggests to me that IBM will try to crank the clocks with Power6+, maybe as high as the 6 GHz target range the company was originally shooting for with Power6 (as far as I know), but the multicore wording suggests IBM might be boosting the core count above the two used in Power6. I haven't said this before, but it is also possible that IBM will boost the number of virtual threads in the Power6+ chip. It could, for instance, keep the cores at two per chip, but boost the threads from two per core to four.

This would not be the first time a vendor took this tack. Sun launched its "Niagara" T1 processors with eight cores and four threads in each core, then boosted that to eight cores with eight threads each with the T2 chips. The future Niagara T3 chips are expected to have 16 Sparc cores, with each core having a staggering 16 threads each, for a total of 256 threads. Pop four of these Niagara T3 chips in a box, and you have 1,024 threads - eight times as many as the top-end Power 595 has today.

Anyway, what we know is that Power6+ is supposed to have twice the performance of Power6, and four times the oomph of the original Power5 chips from 2004. Adding two threads per core and boosting the clock speed to 6 GHz should do the trick, and it won't require a shift to 45 nanometer processes (which IBM may have been originally planning back in 2005). Last summer, when I was thinking about Power6+, I reckoned that IBM would have to double up cores to four per chip and boost the clocks to 6 GHz to double up the performance compared to Power6. But IBM could do thread boosting and clock boosting instead.

IBM could put two whole dual-core Power6 chips into a single package with Power6+, reducing the clock speed to maybe 4 GHz, and boost per-socket performance that way. But I have not gotten the impression that this is where it wants to go. The company did this doubling with the Power5+ quad core modules, and did so because the shift from 130 nanometer to 90 nanometer processes did not yield the clock boost IBM was expecting.

What I do know is that Power7 will have eight cores (and maybe not all of them are Power-style cores) and will be "highly threaded" according to the IBM roadmaps. And rather than test out how to cram more cores onto a die with Power6+ as a dry run for Power7, the company might be adding more threads to test out how to do that best.

No matter what IBM does with Power6+, and when, what is important to Power Systems i shops is that the i 6.1 software stack be tweaked to actually take advantage of the threads or cores or clocks and yield performance increases. (There is little doubt that IBM will do all the necessary tweaks to the AIX and Linux side of the house, but it might be tempted to slack on the i side, since it is a captive base.)

In this economy, the whole shebang had better be attractively priced. Nehalem EP server makers are charging a tiny premium for roughly twice the performance. That is something that IBM has not done since the 64-bit PowerPC AS/400s were launched back in 1995, two years before IBM even had 64-bit RS/6000s in the field. Now would be a very good time to repeat that little bit of history and encourage customers to upgrade to new gear and software. ®

Reducing security risks from open source software

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