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Intel demos Moorestown, embeds Nehalem

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Intel has demonstrated that its long-awaited mobile platform is meeting its power-saving goals, disclosed upcoming low-power Xeon 5500s for storage and blades, and pointed toward a future in which programmers might actually use all the threads and cores the company's hardware is throwing at them.

At IDF Beijing - an event that was cut down to one day due to "current economic circumstances and business pressures the industry is facing globally" - Intel's Ultra Mobility chieftain Anand Chandrasekher demoed a platform designed for mobile internet devices (MIDs) in which the company's new 2GHz Atom Z550 processor and its fellows might find a home.

Codenamed Moorestown, the platform was announced two years ago, but won't see the light of day until 2010. Apparently, a lot of its development time is being spent driving its power needs down - and equally apparently, with some success.

Chandrasekher's demo was a side-by-side showdown between a Moorsetown prototype and a current Atom-based system which showed a greater than 10X improvement in power-miserliness for the upcoming MID platform.

A demo is, of course, merely a demo - but LG Electronics, for one, has already showed enough faith in the Moorsetown platform to announce what it calls a "next generation" Moblin-based MID with phone capabilities, to be released soon after Moorsetown ships.

Pat Gelsinger, SVP and general manager of Intel's Digital Enterprise Group, announced embedded versions of the Xeon 5500 that debuted last week. This embedded-processor line, code-named Jasper Forest and scheduled to appear in early 2010, will be designed for use in NAS and SAN systems, communcations, and what the company refers to as "ultra-dense blades." They'll come in single, dual, and quad-core configs, with power requirements ranging from 23 to 85 watts.

Intel's Larrabee CPU/GPU mash-up also had its moment in the spotlight, with a focus on how programmers might get the most out of this complex, hyper-parallelized beast after it appears in late 2009 or early 2010. Gelsinger pointed out that the C++ Larrabee Prototype Library is now available for help in learning the hybrid chip's new LRBni instructions.

More programming help is coming from what Gelsinger identified as Ct Technology, aka C/C++ for Throughput Computing. This future parallelized-code optimization technology is begin designed for a day when, as Intel predicts, progammers will need to code for hundreds to thousands of hardware threads and thousands of software threads.

As we've noted before, hardware is getting well ahead of software in the new multithreaded multicore world. Here's hoping that Intel's Ct technologists can help - such a development might help lift the industry out of its "current economic circumstances and business pressures." ®

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