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Intel's future Xeons to share sockets

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Exactly how this will translate into application performance will depend on how sensitive those applications are to memory. The Nehalem EP chips, code-named "Gainestown," are expected to come in two-core and four-core variants, with each core having two threads and with either 4 MB or 8 MB of L3 cache. These chips are basically a version of the Core i7 desktop chip reimplemented with symmetric multiprocessing extensions. Clock speeds are expected to range from 1.9 GHz to 3.2 GHz.

The high-end Nehalem EX processors, code-named "Beckton," will have up to eight cores, will be delivered by the end of the year and will use the "Boxboro" chipset that will also be used in the future "Poulson" Itanium processor. The Boxboro chipset will work with QPI to allow a "glueless" SMP configuration with up to eight processor sockets. Technically, the initial Opterons could do this two, by gluing together four two-way motherboards into a single system image, and it looks like Boxboro will glue together two four-socket machines to get an eight-way. The question with either approach is whether server OEMs will do it. Very few adopted the eight-way Opteron configuration.

The low-end Nehalem EN chips are tweaked versions of the Lynnfield chips used in desktops and made with 45 nanometer processes. They plug into a server platform called "Foxhollow" and use the Intel 5 series chipset used on desktops. If history is any guide, these single-socket server boards will have more I/O slots and possibly more main memory than their desktop counterparts.

Looking ahead to the Westmere generation, the future 32 nanometer chips will plug into the Foxhollow, Tylersburg, and Boxboro platforms. This is obviously something that server manufacturers want very much, since they do not like revving their hardware every year. It looks like Foxhollow gets launched in the second half of 2009, and Boxboro at the end of the year, and Tylersburg should have been here already if this roadmap is to scale.

The Westmere kickers to Nehalem EP chips (which have not been given a code name yet) are due around mid-2010, then, and the Clarkdale chip with its integrated graphics processor gets plunked into single-socket servers in early 2010. Don't expect a Westmere kicker to the high-end Nehalem EX until early 2011, it looks like.

The 32 nanometer shrink from Nehalem to Westmere should allow Intel to get clock speeds up around 4 GHz or so, compared to a little more than 3 GHz with Nehalems and their 45 nanometer processes. Or Intel could boost the core count and keep clocks about the same. The expectation is that Intel will go for speed, not cores. But the company could just as easily put two Westmere chips side-by-side in a single package instead of revving the cores, or leave graphics processors into some Westmere Xeons (as it did for the low-end Clarkdale chip) to use as a co-processor for applications.

It would be interesting to see HPC variants of Westmere chips with the graphics units embedded and then two-chip Westmere packages for regular commercial processing workloads. Intel could put other features inside a package as well - or just make the chip smaller and keep the thermals low, offsetting some of the higher heat that DDR3 main memory kicks out compared to DDR2 memory.

Out beyond that, Intel will launch a new "Sandy Bridge" chip architecture in 2010 or 2011 (it depends on the roadmap you look at) with 32 nanometer processes, and it will eventually shrink this family of chips using 22 nanometer processes in 2011 or 2012. ®

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