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Chipzilla sits on its Tukwila

Itanium delayed six months

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Chip maker Intel has quietly copped to another delay with its "Tukwila" quad-core Itanium processors.

The company is revamping the quad-core Tukwila processor design, which will push deliveries of the chip out to the middle of this year. And that means system shipments will be even later. This six-month hold-up is by no means the worst Itanium delay, and it's the smart thing to do.

Tukwila was originally expected in 2006 or maybe early 2007, depending on the leaked roadmap. Then Intel was supposed to have the processors finished and ready to go at the end of 2008, and a handful of OEM partners - including HP, Fujitsu, NEC, and Bull - were expected to begin shipping systems right about now, after a few months of intensive validation procedures.

Somewhere along the line, Intel and its OEM partners decided to ditch DDR2 main memory for Tukwila and switch the chip to buffered DDR3 main memory. This is the same kind that will be used in the forthcoming "Nehalem" line of Xeon servers, also expected to start shipping soon.

The Nehalem servers were originally expected in February and there has been talk that they might ship by the end of March. That date for Nehalem Xeons might not hold - if Intel decides to use the economy as an excuse to delay the arrival of Xeon chips it has already made. Its channel partners may talk it into pushing Nehalems out to mid-year, when the economy might be better.

Anyway, the Tukwila chip has two integrated main memory controllers, and the shift to DDR3 main memory means swapping out the DDR2 memory controllers and plunking down DDR3 replacements. The memory controllers are not integrated into the Itanium cores themselves, which makes this job easier.

The Tukwila memory controllers sit on two sides of a crossbar router embedded into the heart of the chip, linking the cache directories, the caching agents that front end the L3 caches attached to each Tukwila core, and the QuickPath Interconnect ports.

Intel was telling customers they would get about six times the memory bandwidth with Tukwila chips compared to Montvale Itaniums. It is unclear how the shift to DDR3 main memory will affect bandwidth. The Tukwila chip, which has nearly 2bn transistors, will have 30MB of L3 cache on the chips.

Speeds are expected to range from 1.2GHz to 2GHz, and the top-end Tukwila is expected to deliver about twice the performance of the Montvale Itanium 9100 running at 1.66GHz. The fastest parts are expected to have a 170-Watt thermal envelope, which is hot but no worse than big RISC chips with which Itanium competes. They are implemented in a now-old 65 nanometer process, but one that Intel knows how to push to the extremes of yields.

The other big change made on the Tukwila chip was to move it to the same socket type that will be used by the future "Poulson" and "Kittson" Itaniums. The Tukwila chip had its very own socket, which means it cannot be plugged into existing Itanium machines that use the front side bus architecture.

By bringing the Poulson socket forward, Intel's OEMs are going to be able to milk their server designs for the next three generations of Itanium, much as they have been able to do with the last three: single-core Madison, dual-core Montecito, and dual-core Montvale chips (I'm being generous calling Montvale a different generation).

Details on these future Itaniums are thin, but Poulson will have a new "advanced multicore architecture," according to roadmaps, and will be implemented using a 32-nanometer process. Kittson is the ninth Itanium generation, and other than that, Intel has said very little about it.

A year ago, there was some chatter that Poulson might come to market in late 2009 and possibly have six or eight cores. But it would be odd to see Poulson much before 2010 at this point, and it will probably arrive later in the year given that Intel will want to have ramped up the 32-nanometer chip making processes fully before putting Itanium on it. Kittson might appear in 2012 or so.

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Next page: CSI Intel

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