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NAND development axes

There are two development axes as it were - the first is the NAND cell bit density, and the second the process feature size.

Bit density is a measure of how many binary stores there are in a flash cell. A single level cell (SLC) has 1 binary digit. A multi-level cell (MLC) has more with, for example, SanDisk announcing 2-bit cell (2X) products now and 3- (3X) and 4-bit (4X) product coming. If a 1-bit cell chip holds 16Gbits then a 2-bit one will hold 32Gbits, a 3-bit one 48Gbits and a 4-bit one 64Gbits.

A by-product of increasing cell bit density has been a slowing of the I/O write rate with SLC NAND being the fastest and each increase in bit density slowing NAND down. For example. Intel's SLC X25-E SSD does sequential reads at 250MB/sec and sequential writes at 170MB/sec. The MLC X25-M sequentially reads at 250MB/sec but sequentially writes at 70MB/sec, less than half the speed of its SLC sibling.

A second by-product of increased bit density is reduced write endurance. This is being countered by adding parallel channels to controllers and avoiding unnecessary erase-delete cycles when writing data by over-provisioning the NAND and by clever file systems such as SanDisk's ExtremeFFS. This is a uniquely flash phenomenon; it doesn't apply to tape or to hard drives.

Another by-product of increasing cell bit density is to lower the cost per bit of the flash. It's a case of what you lose on the speed and endurance swings you gain on the capacity roundabout.

Process feature size refers to the size of individual NAND cells. The smaller they are the more of them you can fit onto a 300mm NAND flash wafer. That cuts the cost per bit. The smaller they are the more cells you can have in a flash product, such as a Memory Stick, USB thumb drive or solid state drive (SSD). It's reckoned that a move from 56nm feature size to 43nm effectively doubles NAND capacity at any product format. Thus a 32GB SSD with a 56nm feature size will become a 64GB SSD with a 43nm feature size.

There isn't a standard process size at each generation. Toshiba and SanDisk, who jointly operate flash fabs, are moving to a 43nm process size from a 56nm one. Intel and Micron, participants in Intel Micron Flash Technologies (IMFT), are moving from a 50nm process to a 34nm process, bypassing any process in the 40-49nm area. It's expected that SanDisk and Toshiba will progress to a sub-40nm process next.

What looks to be happening is that a given process size starts at 1 or 2-bit and then progresses to 3-bit and 4-bit cell densities. It's expected that the SSD suppliers will be able to maintain an average capacity increase rate by tweaking process size, bit density and chip packaging parameters over time.

Intelligent flash storage arrays

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