Intel to extend chip-tech dominance
Bad news for AMD, IBM
According to an article in today's EE Times, Intel will "extend its lead over AMD, IBM and other microprocessor vendors" at next week's übergeekfest, the 2008 International Electron Devices Meeting (IEDM) in San Francisco.
Specifically, Intel will present papers that detail the company's latest advances in high-k/metal-gate technology, a transistor-manufacturing advantage that has competitors AMD and IBM struggling to play catch-up.
Although the phrase "high-k/metal-gate technology" may sound mind-numbingly esoteric, it's simple in concept - and the fact that Intel's got it and AMD and IBM don't is a powerful plus for the Santa Clara, California chipmeister.
Here's how it works: Simply put, a transistor in any chip is just a switch. Take a light switch, change the names of its parts into chip-speak, and the function of a transistor's gate becomes clear. When you flip a light switch's lever (gate), electricity flows from one wire (source) through the switch's circuitry (channel) to a second wire (drain). To make the switch work, however, there must also be insulation between the lever/gate and the circuitry/channel; in a transistor that insulation is called the gate dielectric.
Still with us? Good, because here's where the aforementioned high-k/metal gate technology comes into play - and why it gives Intel an advantage over other chippies.
As chipmakers have shrunk the sizes of their chips - essentially measured by the distances between transistors - the gate-dielectric insulation layer has shrunk as well. Problem: the thinner a gate dielectric, the more power it leaks, and the more power it leaks, the less efficient the transistor is and the hotter it gets. Both bad.
When chips first appeared back in the 1960s, gates were made of polysilicon, and gate dielectrics of silicon dioxide. At the current process-technology standard of 45nm, those two substances are stressed to their limits - they leak more than a Congressional staffer.
Enter - finally - high-k/metal-gate technology. Back in 2007, Intel replaced the silicon dioxide in the gate dielectric with a metal - hafnium - and the polysilicon in the gate with a proprietary metallic melange. The two substances work togethr to create a gate that has a "high-k," meaning superior insulation performance.
How superior? Intel claims that their high-k/metal-gate technology cuts leakage by about a factor of five. All good stuff.
IBM and AMD haven't kept up. Although AMD's technology partner IBM announced in 2007 that they were thiiis close to achieving high-k/metal-gate success, they haven't yet pulled it off. For their part, AMD's presentations for its 45nm family refer to high-k/metal-gate technology as a "future 45nm option."
While its competitors have been been struggling to get their gate acts in order, Intel has been busy perfecting a second-generation high-k/metal-gate technology in preparation for moving it down to its next-smaller process, 32nm, scheduled for broad release next year.
As if to rub its rivals' noses in the muck of their failure, Intel plans to use the IEDM 's bully pulpit to provide details about that second-generation technology, plus present a paper on their new system-on-a-chip (SoC) designs based on high-k/metal-gate low-power refinements. According to the EE Times article, Intel has "at least four SoCs in the works for systems outside its traditional PC markets. Tolapai is aimed at storage networks, Silverthorne at handhelds, Larabee at high-end visualization systems and Canmore at wired consumer devices." None are yet available for purchase, but they're all under test in Intel labs.
Finally, Intel is also expected to demonstrate its latest bit of wizardry: a high-speed, low-power, quantum-well, field-effect transistor - and as soon as The Reg figures out exactly what the hell that is, we'll let you know all about it. ®
Not to worry everything Intel develops is cross licensed with AMD
Intel and AMD been doing this for years, Intel may do it first sometimes but AMD does it for less cost.
high K is good -- this isn't just about leakage
kevin: almost right, but...
The reason 'k' matters is that the ability of the gate voltage to induce inversion in the channel depends on the gate-channel capacitance. The larger the capacitance, the greater the influence between gate voltage and channel charge. Since gate-channel cap depends on k, high k for the gate oxide is desireable. Lower gate dielectric constant means lower performance transistors.
Low-k is useful in the dielectric between wires where we really need to reduce the effect of a signal on one wire upon the signal on an adjacent wire.
just for the record, the metal gate is made of Aluminium, being cheaper and lower resistance than the horribly expensive Hafnium. Metal simply need to conduct, and to process easily.
Hafnium Oxide, on the other hand, is rather spectacular, withstanding about 20megavolts per centimetre (cf. about 5MV/cm for SiO) - which reduces the gate leakage, and allows the gate oxide to be thinned, (a bit - the leakage through "tunnelling" sets an absolute minimum thickness, process uniformity + tolerance means we never quite get there). the dielectric constant of the gate oxide, the high-k, is not "used" its just that all the exotic oxides have a higher k than silicon oxide, and they chose to characterise the approach based on an inessential parameter.
- if they could get the same dielectric withstand with a lower k then they'd jump at it, lower k means lower gate capacitance equals faster switching.
I think Mr BLoad doesn't seem to understand the concept of the C=kA/D he's spouting.
One should be very careful about calling people Ctards when you clearly don't understand what you're talking about.
Intel are not playing around with D (thickness of the oxide).
In a 45nm process or 32nm process the oxide is already as thin as it will go. The oxide is only a couple of 10s of atoms thick. You can't go thinner, that's it, finito. If you go thinner the oxide does not behave like it does when it's thicker. At these thicknesses quantum effects kick in and electrons can jump across the oxide without it breaking down and the leakage current goes through the roof. So unfortunately D is fixed.
A or the area gets scaled down when you go from 45nm process to 32nm process etc otherwise what's the point. In order to maintain a useable capacitance then the only factor in the equation that can be adjusted is "k". Which is changed by using different materials for your dielectric. That's why they're call high "k" materials, as the "k" factor needs to be increased.
Hafnium metal gates are required because the speed of operation of the transistor is a factor of the resistance and the capacitance. Using a different metal increases speed. Increases cost too.
There are many many many papers on this stuff available from the IEEE just search. (Very technical though) I've simplified it as much as possible.
Fair play to intel. The whole metal gate High K dielectric problem is a really really big one. The reliability of the dielectric is of special concern. You can't use any old common or garden Hafnium oxide mush as your insulator.
The fact that intel have solved this, is a major achievement.