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AMD beats drum for Shanghai surprise

Anyone seen Big Blue?

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Struggling x64 chip maker Advanced Micro Devices has told platform suppliers it's a good time to talk about the imminent launch of "Shanghai," a 45 nanometer implementation of its quad-core Opteron chips for servers and workstations.

You have to guess on when "imminent" might be, because AMD hasn't confirmed the Shanghai launch date. But next Thursday (November 13) is AMD's annual Financial Analyst Day shindig, where an exhausted, distracted, and battered Wall Street will try to pay attention to whatever future AMD lays out as they watch their portfolios bob up and down with the minutes and hours, polish up their resumes, organize their iPods, and perhaps ponder what it might be like to run a restaurant or a small organic lettuce farm.

The Shanghai Opterons and AMD's plans to divest itself of its chip fabs will be the main topics of conversation at the analyst event, so it is not hard to figure out when Shanghai will debut.

As we previously reported when AMD started talking up its revamped Opteron roadmap back in September and the fact that it was able to get Shanghai out earlier than expected, the Shanghai Opterons are four-core kickers to the current "Barcelona" Opterons.

The Shanghai Opterons, being manufactured in a 45 nanometer immersion lithography technique, can cram more transistors and therefore more features on a chip than was possible with the Barcelonas, which were implemented in a 65 nanometer process. The shrink allows for higher clock speeds as well. All AMD has said publicly is that the Shanghai chips will have 6MB of L3 cache and clock speeds that are higher than the current top-end 2.3 GHz standard Opteron parts. Barcelona Special Edition chips are also available at 2.4 GHz and 2.5 GHz.

Back in September, AMD said that with higher clock speeds and tweaks in the instruction stream, Shanghai chips would deliver somewhere between 15 and 30 per cent more performance compared to equivalent Barcelona chips. And then it hedged and said customers should expect around a 20 per cent boost for an average workload. On a conference call with tier-two system vendors today, Burke Banda, product marketing manager for AMD's Server and Workstation Division, said that early tests by system vendors showed Shanghai delivering about 35 per cent more performance and that the newer chips consumed about 30 per cent less power.

Banda said that AMD has a "decided advantage" in the four-socket server space compared to Intel's new quad-core and hex-core "Dunnington" Xeon chips - and that it will have a "time to market advantage" compared to Intel's future "Nehalem" Xeons, due next year in servers. "It is a very well-rounded product line for right now," Banda explained.

The Shanghai Opterons will support 800-MHz DDR2 main memory, and plug into the existing Socket F1 CPU sockets. (They are also called the Rev F socket or the Socket 1207). Next week, if the rumor mill is right, the 75 watt standard Shanghai parts will be launched. These will be followed in the first quarter of 2009 by Highly Efficient chips, or HE for short, designating 55-watt parts and Special Edition chips, or SE for short, which means chips running at slightly higher high clock speeds and pumping out 105 watts.

The Opteron 1000 Series variant of Shanghai, known as "Suzuka" and plugging into the AM2 socket, is due in the second half of 2009. Existing nVidia nForce 3050 and 3600 chipsets and Broadcom HT-1000 and HT-2100 chipsets will support the Shanghai chips. In the first half of 2009, AMD will bring out its own chipsets in what AMD is calling the "Fiorano" platform. (See the previous story for details.)

The other feature that the Shanghai chips will have is that they will be "priced aggressively," according to Banda. Just how aggressively remains to be seen, but AMD can only cut so deep. With a big performance boost, chip makers are often tempted to price based on performance, which means per-chip prices often don't fall as far as you might expect. Customers end up paying for the extra performance.

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