A year ago, at the annual Hot Chips conference for chip designers in Silicon Valley, a company called Tilera came out of stealth mode and launched its 64-core Tile64 mesh processor. The Tile64 chip takes multi-core to an extreme, and an on-chip iMesh network allows a grid of cores and memory controllers to compete with X64 or DSP processors doing a variety of work.

This week, Tilera is putting its second-generation chips into the field and is getting some traction among various IT suppliers, who want to put the Tile64 processors and their homegrown Linux environment to work.

Before getting into the changes in the new TilePro chip, let's review the first-generation device. The Tile64 core was a 32-bit design (with a 16-bit mode) that employs RISC and VLIW concepts. It can do three instructions per clock cycle, and the chip's speed ranges from 600 MHz to 1 GHz. The Tile64 chip has 64 KB of L2 cache as well as L1 data and instruction caches that are 8 KB in size each.

The switch that is at the heart of the Tile64 processor actually implements five different mesh networks - one each for memory access, streaming packet transfers, user data network, cache misses, and interprocess communications. Wrapped around the cores are four DDR2 main memory controllers, two Gigabit Ethernet ports, two PCI Express controllers, two 10 Gb/sec XAUI interfaces, and two flexible I/O interfaces to support peripherals such as compact flash memory or disk drives.

The whole shebang is implemented in a 90 nanometer process and made by Taiwan Semiconductor Manufacturing.

The Hardwall

The Tile64 design is clever in a number of ways, which means it might see some use in IT devices near you someday soon. First, it does not use a bus architecture to talk to peripherals or to have processors and cache memory talk to each other. The iMesh network allows point-to-point communication between the chips and does away with bus architectures, which require high clock speeds and lots of energy to deliver bandwidth and scale.

The Tile64 chip also uses the mesh network so L2 caches on each core can be used like a giant L3 cache in a traditional design. Basically, any core can look into the L2 cache of any other core on the chip and treats that like a giant 5 MB L3 cache. While each core on the Tile64 chip can run its own complete instance of Linux, the cache coherency engendered in the mesh network means that a collection of cores can be setup to run an SMP setup of Linux, too.

The iMesh network controls all communication into and out of a core, a microcode feature called Multicore Hardwall Technology can partition a Tile64 into multiple virtual machines, allowing different instances of Linux and their applications to run on the chip and be isolated from each other. The Tile64 chip supports a variant of the Linux 2.6 kernel and has a tweaked version of the open source GNU C compiler and the open-source Eclipse integrated development environment.

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