IBM gets virtual and cloudy with 22nm chips
X-ray vision still missing
IBM may not be in the same league as Intel when it comes to volume chip production, but the PowerPC family of chips gets embedded in all kinds of devices, and it does a decent volume with its related Power chips in servers, too. Plus, the company sells intellectual property related to chip making. And that is why IBM needs to show now that it has the future chip fabrication processes that processor outfits can depend on for their future products.
To that end, IBM this week introduced a set of technologies that it is collectively calling computational scaling, or CS. These technologies will get the company's chip fabs down into the 22 nanometer size range for circuits by late 2011. IBM is partnering with Mentor Graphics and Toppan Printing to get there.
At the moment, IBM is rolling out 45 nanometer processes in its East Fishkill, New York chip plant, which is where its Cell, PowerPC, and Power6 processors are currently made. That process is based on a technique called immersion lithography, which is important because conventional lithographic chip making methods hit a wall at 65 nanometers.
With immersion lithography, the laser light beams that are used to etch circuits into photosensitive material on silicon wafers are focused by a layer of water that surrounds the wafer. Because light slows down when it enters the water, you can crank the light up to a higher frequency, which yields a tighter laser beam - and the ability to etch smaller circuits.
IBM is ahead on the water immersion technique, but according to Kevin Warren, director of design and technology integration at IBM's Semiconductor Research Center, the entire industry will be using it for their 32 nanometer chips.
If this water-immersion technique didn't work, the industry would have probably moved to X-ray lithography, which would be a very expensive move. Bathing wafers in water before you etch them is a lot cheaper. And, besides, Warren says the X-ray techniques - which are sometimes called extreme UV lithography, or EUV - are not working properly yet. At least not at prices that chip makers or their customers can bear.
In fact, says Warren, it was these very EUV techniques that IBM and its partners - as well as other chip makers - that were expected to help make the jump from 32 nanometer to 22 nanometer circuits. Now, IBM is hoping this EUV technology will be ready for prime time for 15 nanometer circuits. It takes about five years to get a chip making process from the development lab out into the factory. So the delay in EUV technology is a big problem for something that was slated for late 2011.
"Now we have to find other knobs, other optimizations, to get scaling," says Warren. And, of course, IBM thinks it has come up with some tricks or it would be quiet as a church mouse.
Mentor Graphics has been an IBM chip partner since the company was making 130 nanometer chips in the Power4 generation back in 2001. (That was the first dual-core chip in the industry, and the chip that put IBM on the road to equality with Sun Microsystems and Hewlett-Packard in the Unix server space). Mentor has a set of software called Calibre that is, for lack of a better metaphor, akin to a CAD system for lithography.
The Calibre software is able to take the designs for chip masks and, knowing the physics of light and water, it can distort the masks from their intended designs such that features that would normally be blurred by the very physics of the light beams, water, and semiconductor material are instead sharpened. (Neat trick, huh?)
This is called source mask optimization, and it is a key technology in IBM's move to 22 nanometer circuits. IBM has also partnered with Toppan Printing for the past three years to come up with techniques to increase the resolution of photomasks and to make them easier and quicker to make.
One of the new technologies that IBM is cooking up for computational scaling is called the Virtual Fabricator. (This is the virtual and cloudy part). Rensselaer Polytechnic Institute, the engineering school located in IBM's home state, has worked with the company that takes the simulation that has been used for decades to design chips one step further. It actually simulates the entire chip making plant, right down to the masks and the etching. The idea is to find out where the bugs are years in advance of when the chip plant is trying to move into production.
Rather than hoard this technology, Warren says that IBM will make it available to the industry. "We intend for this 22 nanometer technology to be a standard, not something we hold onto ourselves." Of course, that tech will come at a price - and we ain't talking cheap. ®
Sponsored: Global DDoS threat landscape report