New 3D chip transistor may reach 50GHz
Japan and Singapore firms make R&D pact
Japanese R&D firm Unisantis says it will create and sell a new kind of "3-D" transistor that provides 10 times the computing speed of current chips.
It is entering a 24-month collaborative agreement with Singapore's Institute of Microelectronics for simultaneous design work.
The companies claim processor clockspeeds could reach between 20GHz and 50GHz by using a 3-D structure that arranges components vertically, as opposed to the horizontal design of our forefathers. The device is dubbed the Surrounding Gate Transistor.
And just as the alarming appearance of a sphere confounds — and yes — frightens a resident of Flatland, so shall the eldrich machinations of this 3-D transistor do unto this Register hack.
But rest assured brighter minds are on the case.
The design work is headed by CTO of Unisantis Fujio Masuoka - a man credited with the invention of flash memory. He'll be joined by some 30 academics, engineers and scientists on the project.
According to Masuoko, SGT is a vertical silicon pillar surrounded by memory cells, electrical contacts and various other unnamed components (our guess: the screeching souls of the damned).
The 3-D structure apparently reduces the distance that electrons travel, generates less heat and costs less to produce than existing chips.
"The SGT also allows further improvements in silicon-based semiconductors, in terms of transistor size and processing speed, for at least 30 more years before the theoretical limits are reached. Such improvements are necessary for new-generation IC chips to meet the computing power demanded by IT products and computing networks of ever-increasing functionality and complexity," said Masuoka. ®
Not 3D Chips
The chips aren't going to be 3D! You won't have more than a single layer of transistors*. It's just that the individual transistors will have a more 3D structure. Modern CMOS transistors aren't exactly 2D either mind. *Most* of their characteristics can be modelled by assuming they have a constant cross section - but not all. Hence TCAD simulations of devices are moving from 2D to 3D. This sounds like just another variation on the FinFET idea.
Also remember kids - Moore's Law predicts the performance to cost ratio. Technologies like this (and even 'conventional' CMOS nodes approaching 32nm) may be possible but are likely to be very expensive to develop and produce.
* There isn't much point in putting multiple layers of transistors on a chip. The number of processing steps require multiplies so the cost does to (and some). It already takes hundreds of processing steps to make a CMOS wafer. The cost performance ratio doesn't really improve. There are also problems with heat dissipation, process integration, failure analysis and interconnect. The only advantage is less clock skew, but that has already been worked around by having the multiple clock domains of multi-core designs.
3D is the way to go...
... everybody says that, but there are two problems to solve before: how to build the things in the first place (as it is now with only 7-8 layers, you already get enough duds ) and how to cool transistors in the centre of that structure.
@auser: silicon dioxide is on the way out, high-k dielectrics based on hafnium are all the rage these days.
Not bad but..
I'd put a big clock on it and overclock that sucker!
Currently the fastest working cpu is around 10Ghz and made by ibm. Intel works on a similar design and it's fastest cpu is around 8Ghz. Packing transistors in a vertical fashion is not new and the elimination of metal wires between transistors could make systems both faster, smaller and less hot. All you need is a way to put multiple layers of conducting silicium and insulating silicium dioxid on top of each other. Adding metal oxid gates to this technology could result in systems around 100 Ghz, with 1 Thz attainable in research labs. Apparently Moore's law is pretty much still works...
"The 3-D structure apparently reduces the distance that electrons travel, generates less heat and costs less to produce than existing chips."
Hmmm, sounds like the classical "too good to be true" moment... But if the inventor of flash memory is behind it, then I guess we can hope.