AMD denies 'stop ship' with Barcelona because chip is not shipping
Even though it is - with a bug
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Since its launch, AMD's four-core version of Opteron known as Barcelona has lived in what you might call a processor protection program. The chip is apparently available in quantity, according to AMD, but customers struggle to find it.
Now AMD has confirmed that an erratum or bug in Barcelona needs to be dealt with before the chip can reach a mass audience. Customers in the high performance computing market will be taken care of now, but the Average Joe won't see a four-core Opteron until next year.
Some reports out there say that AMD has halted shipments of Opteron altogether because of the bug, although a company spokesman denied those claims.
"We haven't changed the shipping pattern," AMD man Phil Hughes told InternetNews. "It's only a stop ship if it's shipping in volume, and we're only shipping Barcelona for specific customer commitments, like larger volume deployments."
AMD seems to be fiddling with language, as far as we're concerned.
For one, we're told that this isn't a "stop ship" because as far as AMD is concerned it's not really shipping the products. Erm, ok.
In addition, during a recent earnings call, AMD executives talked about shipping thousands upon thousands of units this year. They also confirmed the arrival of speedier versions of Opteron in 2007.
Shortly after the call, however, we discovered IBM pulling Opteron-based server benchmark results because it could not ship the systems in the required amount of time to meet the policies set up by SPEC (the Standard Performance Evaluation Corp.). So, IBM certainly faced a change in its expected "shipping pattern."
Our readers too have complained of Barcelona's absence from major vendors' server price lists. That's a heck of a note after AMD rolled out every partner it could find at the Barcelona launch event, giving the impression that you could actually buy the gear.
It seems now that all of the Barcelona chips are heading to supercomputer-class installations where millions of dollars and bragging rights are at stake.
AMD needs extra Barcelona delays like it needs the financial and personnel pains associated with swallowing a large graphics chip maker right now. Intel has just pumped out a new fleet of faster, more energy-friendly Xeons and plans to boost its product line in a more aggressive way next year.
All told, true volume shipments of Barcelona look set to occur about a year later than AMD once planned.
The most detailed technical information on the bug attacking Opterons comes from The Tech Report.
To recap, the erratum is a chip-level issue involving the TLB logic for the L3 cache that can cause system hangs in specific circumstances. AMD has a fix for the problem in the works, but it degrades performance. AMD has stated publicly that the workaround can lower performance by as much as 10 per cent, although one source characterized the performance hit to TR as 10-20 per cent.
The bug also effects Phenom chips, as Register Hardware reported last month.
"There has been some talk about an erratum relative to our TLB cache in Barcelona as well as Phenom processors resulting in delays," Hughes told PC Mag. "AMD notified customers of this erratum and released a BIOS fix prior to the Nov. 19th launch that resolves it. We are experiencing strong AMD Phenom demand and are shipping parts to channel, system builders and OEM customers."
Hughes added: "You may remember that during our Q3 earnings call, AMD acknowledged that our initial ramp of Barcelona had been slower than anticipated. However we did say during that call that we would ship 'hundreds of thousands of quad-core processors' into the server and desktop segments during Q4. AMD is tracking to this guidance." ®
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COMMENTS
Translation
AMD:
"we're only shipping Barcelona for specific customer commitments, like larger volume deployments."
Translation:
"We busted a gut to try and get 16,000 chips together so that the Ranger supercomputer at the Texas Advanced Computer Centre could deploy in time for the November Top500. Now we've missed that deadline everyone can wait until we get it sorted out properly."
Re: TLB for the 3rd Level Cache
Chris wrote:
"A 20% decrease in performance just to fix a TLB bug in the 3rd Level Cache. I would doubt removing the 3rd level cache would even cause a 20% performance hit."
I'm guessing that the BIOS workaround had to disable some other stuff as well to stop the system crashing which had a big performance impact.
When the chips are fixed and everything can be turned back on then the performance impact will probably be much smaller.
Clarification
Thanks for clearing that up (regarding Old News).

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