Sorting through Intel's SoC drawer
'Canmore' and 'Tolapai' - compare and contrast
IDF Intel launched its first foray into the world of system-on-a-chip (SoC) products for consumer electronics kit in April this year. Then, at its Spring IDF conference, it launched the CE2110, an ARM-based CPU with a built-in graphics engine, memory controller and more.
At the time, Intel's Digital Home Group chief, Eric Kim, mentioned that the chip giant would next year offer an updated SoC based not on ARM CPU technology, but on its own x86 instruction set, as used in all its desktop and mobile processors.
Six months or so on, at the Autumn IDF, Intel CEO Paul Otellini put a name to the project - 'Canmore' - and said it would make its first public appearance in January 2008 at the CES show.
Intel's CE2110: what's inside
Like the CE2110, Canmore is aimed at TVs and set-top boxes. The current chip combines a 1GHz processing core with a memory controller; a PowerVR MBX Lite GPU; controllers for USB, SATA, PCI, smart cards and other ports and interconnects; decoders for MPEG 2 and H.264 video; digital and analogue display drivers; a transport stream handler; TV descrambling circuitry; and an AES encryption module.
Canmore is likely to contain all these elements - Otellini mentioned the chip's AV pipeline, GPU, I/O components and a security sub-system - with a low-power x86 core, possibly based on the 45nm 'Silverthorne' CPU Intel is developing for UMPCs and mobile web gadgets.
As we've noted before, the SoC now known as Canmore will be the natural heir to Intel's ill-fated Pentium III-based SoC, 'Timna', announced in the late 1990s but never released as a product.
How much technology Canmore shares with 'Tolapai', the enterprise-oriented SoC Intel revealed at Spring IDF and which also got a mention at this week's event, remains to be seen. Again, Tolapai combines an x86 processing core, memory controller, an I/O controller and - first mentioned by Intel this week - a unit called the QuickAssist Accelerator.
Intel's 'Tolapai': for workstations, not tellies
The QuickAssist Accelerator ties the SoC into Intel's QuickAssist Architecture, its framework for application-specific co-processors that connect to the host computer's CPU via the standard frontside bus. This is not so very different from what AMD is proposing with its Torrenza programme, which, in part, is about establishing a framework for application accelerators that connect to the AMD CPU via the HyperTransport bus.
Intel's own take on HyperTransport, QuickPath Interconnect, is due to debut late next year as a key element of its 45nm 'Nehalem' processor architecture, and the use of the 'Quick' prefix - QuickPath, QuickAssist - may not be entirely coincidental.
Incidentally, Intel and IBM are working to deliver the same kind of approach, but using PCI Express add-in cards. That project, codename fans, is called 'Geneseo'.
Canmore, of course, doesn't need any of this, so is likely to come to market much sooner than Tolapai, especially if Intel's keeping the enterprise SoC waiting in the wings until Nehalem-based machines debut at the end of 2008.
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