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Tosh talks up Flash chip stack tech

Through-silicon vias to boost storage capacities

Gartner critical capabilities for enterprise endpoint backup

Toshiba has applied the through-silicon via (TSV) technique - chip makers' flavour-of-the-month technology - to boost the capacity of NAND Flash chips with only a "minimal" increase in chip size and no need for a new fabrication node.

Announced today at the VLSI Symposium, held in Kyoto, Japan, Toshiba's new Flash structure places multiple layers of electrode material and insulating films one on top of the other, drills many parallel holes down through the stack then fills the holes with electrode pillars. Where each pillar crosses each the electrode layer you get a memory cell. Increasing the number of pillars and the number of layers boosts the storage capacity of the structure.

Toshiba's stacked Flash tech
Toshiba's Flash stack tech: the basics

Toshiba claimed its approach is easier to manufacture than a structure built by stacking traditional 2D Flash arrays. Chip size doesn't increase as much as it would with this latter approach because pillars that link through to peripheral circuitry can be shared.

Toshiba's new method has a Sonos structure - silicon-oxide-nitride-oxide-silicon. The electrical charge is held in the silicon-nitride film, which is formed inside gate holes. Traps are formed to lock the electrical charge inside the silicon-nitride film, Toshiba said.

Toshiba's stacked Flash tech
Toshiba's Flash stack tech: in detail

Toshiba's announcement comes two months after IBM, Intel and Samsung all separately said they would be using TSVs to increase the density of a variety of chip types, from SDRAM memory to microprocessors.

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