High fiber diet gives Intel 'regularity' needed to beat AMD
Smooth and prosperous
IDF Intel yesterday wowed server enthusiasts with some Metamucil inspired messaging and a host of new goodies designed to expand the chipmaker's reach.
We'll hit the goodies first and then return to the Metamucil and Intel's regularity.
The initial item to jump out at us came during server chip chief Pat Gelsinger's keynote. The chipper fella updated the Intel Developer Forum crowd here on an ongoing effort to mimic AMD's FPGAs in Opteron sockets agenda.
At the last IDF, Intel revealed it has formed partnerships with FPGA makers Xilinx and Altera to create products that fit right into Xeon sockets. Both FPGA makers have already been working with start-ups DRC and XtremeData to make similar gear for Opteron sockets, which is available today. The idea is that high performance computing types, oil and gas firms and financial services companies can program the FPGAs to handle specific software loads and speed up the performance of their code.
Intel has now signed up XtremeData as a partner as well. More importantly, Gelsinger bragged that HP, IBM and Rackable Systems are all behind the FPGA push.
This is a pretty astonishing move by Intel, which has maintained strict control over what touches its precious sockets, and it took a more powerful AMD to break Intel's socket stranglehold.
Gelsinger also showed off something Intel is calling "Tolapai." This product is billed as a "system-on-a-chip" aimed at appliance makers. The part, due out in 2008, contains an Intel-based core, a memory controllers, IO controller and Intel's QuickAssist Accelerator technology. Appliances using the chip will handle things such as XML and encryption processing.
We've got more on the technology here.
Intel also hyped 3-D memory technology to be used with its chips containing tens of processing cores.
Keeping such chips fed with memory proves tough, so Intel has decided to lay memory right on top of the processing cores and connect the parts with "copper bumps" that create an electrical bond.
Intel Broke Me
"The signal and power move through the lower die to the upper die in the stack," Gelsinger said.
Last but not least, Intel bragged that its upcoming 45nm Penryn processors have outperformed 65nm Xeons in the lab by at least 25 per cent on some Java applications and up to 45 per cent on HPC workloads.
And now to the regularity.
Full of fiber
Intel CTO Justin Rattner's speech went all over the place with the executive spending most of his time in discussions with various Chinese executives. Our Chinese being what it is, we struggled to share in Rattner's enthusiasm.
(Incidentally, Rattner, Gelsinger and Sun's David Yen were all on our flight out here. The Intel executives do not fly economy, as has been claimed.)
Rattner pointed out that Intel's new Fab68 in China was so named because "six stands for smooth sailing and eight stands for prosperity."
Those are just the types of qualities Intel is hoping for in the coming years after having suffered through a horrible 2003-2005. Intel's roadmaps during that period looked less like the work of engineers and more like the work of Jackson Pollock with a host of chips crossed out, others delayed and new chips added in to help Intel compete with AMD.
The Intel Dancers of Regularity
These days Intel spends a punishing amount of time talking about its "regular cadence" of product delivery and its "tick tock" approach to manufacturing and processor design. Were you to drink every time Rattner said "regular," "cadence" or "literally" you'd soon feel worse than we did during his keynote.
"We are on a regular rhythm – almost a heart beat," Rattner said. "As a developer, you can expect that rhythm."
Emphasizing this point, Intel's slideware pointed to an article from the Highly Reliable Times that talked about how reliable its chip production methods are. Seriously.
To be fair, Intel's roadmap does seem much more like a well-working bowel than a Pollock painting these days.
It has plenty of chips coming to feed the mainstream notebook, desktop and server lines – yes, Gelsinger spent 45 seconds on Itanium as well. And along with this flagship gear, Intel has done its own R&D work or recruited partner help with accelerators, memory breakthroughs and the like. ®
Sponsored: DevOps and continuous delivery