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AMD next-gen chipset roadmap leaked?

HyperTransport 3 and PCI Express 2 goodness

Gartner critical capabilities for enterprise endpoint backup

AMD's plan to introduce HyperTransport 3-equipped processors - the so-called 'star' line, thanks to their astronomy-inspired codenames - in the second half of this year is well known. So it should come as no surprise that the company is readying HT3 chipsets to the same schedule.

According to alleged roadmap information, published by Spanish-language site Chile Hardware, H2 2007 will see a trie of chipset releases: the high-end RD790+, the mid-range RX740+ and the budget RS740+. The plus suffix is almost certainly a reference to the use of the updated Socket AM2+ interconnect.

All three North Bridge chips will be accompanied by AMD's existing SB600 South Bridge. The RX740+ is described as a PCI Express 2.0 part supporting a single x16 connector for graphics - but without an integrated GPU, unlike AMD's current mid-range chipset, the RS690, shipping as the 690G.

Curiously, the top-of-the-line RD790+ - which will be a dual PCIe x16, CrossFire-enabled part - isn't described as supporting PCI Express 2.0, as you might well expect such a board to be. Certainly, Intel's upcoming range-topping X38 chipset will support PCIe 2.0. The RD790+ is also said to support four x8 PCIe connectors, suggesting a 'Quad CrossFire' option.

Moving into H1 2008, we should see the introduction of the SB700 South Bridge, the report indicates, appearing in the RS780 chipset. This mid-range part does incorporate a GPU, a DirectX 10 unit that also features AMD's Universal Video Decoder core, apparently. Again, the RS780 is a PCIe 2.0 part. It's said to be scheduled to be fabbed at 55nm.

The SB700 has ports for 12 USB 2.0 devices, two USB 1.1 add-ons, six SATA drives, parallel ATA and PCI add-ons. It also has the usual power management and HD audio support. Interestingly, the reference design also incorporates a Flash module on the ATA bus - presumably to support Windows Vista's ReadyDrive Flash cache technology.

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