In the Spring of 2000, Intel confirmed it was working on a range of SoCs, of which Timna was merely the low-end version. Timna was demo'd for the first time in public. At the time Intel called it a "smart integration product". Pat Gelsinger, then the chip giant's CTO, said the SoC's memory controller would initially use SDRAM, with RDRAM support coming in 2001. This would, he said, begin "the transition of RDRAM into the value segment".
By now, Timna was being stated on leaked roadmaps to debut at 666MHz. A 700MHz version would also ship later in 2000. At the Computex show, held in Taipei in June, we even saw some Timna-oriented motherboards. That said, whisperings around the show alleged Timna was being delayed, to Q1 2001. There were problems, it was claimed, with the SoC's memory hub technology. It was inefficient, and Intel needed more time to fix it.
Then, in October 2000, Intel confirmed it had knocked Timna on the head. The Memory Translator Hub, used to connect the chip to SDRAM rather than RDRAM - as Gelsinger had promised the previous Spring - had proved to be a flawed design, it was alleged. With SDRAM appearing more viable in the longer term than RDRAM, especially at the low system price-points Timna was to have targeted, Intel may have tried to shoehorn SDRAM support onto the SoC, with disastrous results.
And in any case, Intel was eyeing up the possibilities a dedicated notebook processor would bring it. Why pitch for a business predicated on low-cost - and therefore low-margin - PCs, when it could target the high-margin but rapidly expanding laptop market?
Enter the development effort that would produce 'Banias', Intel's first notebook-specific processor and the basis for its Centrino platform. Both were launched in Spring 2003, but early details began to appear in early 2001, exactly the timeframe the delayed Timna was due to have appeared.
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