Intel 45nm CPUs to use metal gates, high-k dielectric
One step ahead of the competition
Posted in Servers, 27th January 2007 05:02 GMT
Free whitepaper – Cooling strategies for ultra-high density racks and blade servers
Intel's 45nm microprocessors will incorporate transistors constructed with metal gates and high-k dielectric materials, the chip maker revealed today. That said, it was tight-lipped about which materials will actually make up these components in its 45nm dual-core die, 'Penryn'.
Penryn's transistors use a metal in place of the polysilicon material that controls the flow of current through today's transistors. And where standard processor transistors separate the gate from the source and drain, and the silicon substrate all these elements are mounted on, Penryn's transistors will use a high-k oxide.

The upshot, Intel claimed, was a "significant performance increase and leakage reduction" - less power is required to switch the flow of electrons through the transistor on and off. Leakage - the flow of current outside the transistor - is reduced, Intel said, because the use of a high-k material means the oxide layer can be thicker than is currently the case, making it harder for electrons to leak through. The high-k material is derived from Hafnium, but Intel would say no more.
It said the new transistor construction will see source-drain leakage reduced fivefold and gate oxide leakage tenfold. Or Intel can opt to raise the drive current 20 per cent, boosting the transistor's switch speed, which essentially means faster processing. Those figures are relative to a standard transistor rather than the design implemented in Intel's 65nm transistors, which included a low-k gate oxide.
Intel also claimed the metal gate and high-k combo would yield around a 30 per cent reduction in the power needed to switch the transistor.
Intel has been working on high-k dielectrics since 2003 at the very least, though it's a technique arch-rival AMD has in the past poo-poo'd. It has put its faith in silicon-on-insulator (SOI) technology and a three-gate transistor design.
Free whitepaper – Deploying high-density zones in a low-density data center

Analyst Keynote: The Register Agile Data Center Summit
Seven ways to lower storage costs
Dell PowerEdge M710 with Dell EqualLogic storage vs. HP ProLiant BL685c with HP StorageWorks EVA 4400
Analyst Keynote: The Register Agile Data Center Summit

Vint Cerf mods Android for interplanetary interwebs
Adaptec CEO on the ropes after dreadful results
Boffins working on biodegradable flexi LED implants
Nvidia taps Transmeta team for x86 chip, claims analyst