AMD's quad-core processor will become a dual-core processor if it decides the user isn't giving it enough work to do. The chip will also beef up the on-board cache with an extra level of memory shared between the four cores.

So reveal company next-generation architecture slides posted by HardOCP. Dubbed "ideal for 65nm SOI and beyond", the native quad-core die's four processing units are surrounded by an "expandable shared L3 cache". Each core will feature "improved branch prediction", the ability to do two 128-bit loads per cycle feeding into a "dual 128-bit SSE dataflow", and can execute up to four double-precision floating-point ops per cycle.

Updated on-board North Bridge components include four "ungangable" x16 HyperTransport links for up to 5.2bn transfers per second. AMD's slides also point to "next-generation memory support" including FB-DIMM support "when appropriate". As we've seen before, AMD expects that to be when the memory costs as much as DDR 2 does today.

More interesting is the quad-core processor's power management system, dubbed Dynamic Independent Core Management (DICE), which not only throttles back each core's clock frequency according to need but can also halt cores entirely to conserve power further. At what point the power management system decides to temporarily shut down one core or more isn't made clear.

More to the point, perhaps, how much of this will make it to the quad-core chips that AMD will actually ship remains open to question. Upon close examination, the slides are revealed to be dated 21 August 2005, and in the intervening 12 months AMD is likely to have revised the design of its quad-core architecture. ®