AMD, IBM 'stress' silicon for 65nm chips

Technique boosts transistor performance 40 per cent

Security for virtualized datacentres

AMD and IBM yesterday claimed their take on the 'strained silicon' technique had yielded a 40 per cent boost to transistor performance.

The two chip-making partners will introduce the technology into their 65nm fabrication process, which in AMD's case is expected to go into volume production next year.

'Strained silicon' is the process by which the lattice of silicon atoms in a semiconductor are pulled further apart than usual in order to improve the flow of electrons between them. Intel has been using the technique for some time. AMD introduced it in its 90nm process.

As with previous implementations of the technique, AMD and IBM's 'stressed silicon' process uses Silicon-Germanium (SiGe) to stretch a layer of pure silicon. The SiGe atoms are further apart than the silicon's, which stretch to align themselves with the SiGe lattice. The SiGe layer is applied to the insulating material used as the basis of the two firms' silicon-on-insulator process. Once the silicon lattice has been stretched, the SiGe layer is removed. The interaction of the insulator and the silicon helps retain the wider atomic spacing, a techique the companies call Stress Memorisation Technology.

AMD and IBM also said they were implementing lower dielectric constant (low-k) insulators into the 65nm process to "reduce interconnect delay" and "improve overall product performance and lower power consumption".

AMD and IBM have been co-operating on 65nm and 45nm fabrication technology since January 2003, and have renewed their development agreement several times since. Last month, the pair formally agreed to extend the partnership out into the 32nm and 22nm eras. ®

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