IDF Intel today confirmed that 'Yonah', its 65nm dual-core mobile processor and the basis for the 'Sossaman' low-power Xeon chip, will support Virtualisation Technology.

The chip will also feature a dynamically allocated 'smart' L2 cache shared between the two processing cores. Dubbed 'Smart Cache', the system gives both cores access to the full 2MB of the eight-way associative L2 cache, dynamically adjusting the area allotted to each core. The reason: to minimise the performance hit from single-thread apps. Data can be shared efficiently between threads.

When the processor load falls, Yonah gradually flushes the L2 cache, synchronising it with main memory. The unused cache is turned off, physically as well as logically, to reduce power consumption.

Intel also said Yonah has an Enhanced Deeper Sleep mode, which kicks in when the cache is empty so the cache voltage can be lowered beyond that needed to sustain data within it - ie. the level of the standard Deeper Sleep mode.

Yonah has a new instruction to allow the host OS to shut down each core separately, to reduce power consumption when the load is low.

Sossaman takes Yonah and adds dual-processor support, along with a 36-bit physical address bus to allow the chip to handle up to 64GB of physical memory - typically 400MHz ECC DDR 2, connected via the E7520 'Lindenhurst' chipset Intel expects Sossaman to be used with. That said, the E7520 supports only 32GB of RAM, so the gain is moot.

Past Yonah announcements have revealed the chip will support ten of the SSE 3 instructions, and extend its micro-op fusion technique to take in SSE 2 load instructions to boost performance - the better to improve the part's media processing performance, the big difference between Pentium M and NetBurst-based chips. The chip's floating-point performance has also been tweaked, with enhanced data pre-fetch. ®

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