Otellini stakes low-power future on strained silicon
Chipset 'shortage' too
IDF Intel's strained silicon process will stand it in good stead through the next four generations of the chip giant's processor products, Intel CEO Paul Otellini claimed today.
He also signalled the end to the current capacity constraints affecting the company's chipset production.
Speaking to reporters after his Intel Developer Forum keynote, Otellini rejected the suggestion that the company's plan to boost processor performance while simultaneously reducing power consumption would force it to embrace silicon-on-insulator, as arch-rival AMD has done.
"We're not going to use SOI," he said. "We can do this without the cost and complexity of adding SOI, not for the next four generations, in particular with what we're doing with strained silicon."
Intel's process roadmap calls for a shift to 65nm in 2006, followed by a move to 45nm in the 2008 timeframe. Otellini re-iterated Intel's expectation that in Q3 2006, 65nm output will overtake 90nm production.
Otellini said there was a "significant" drive to roll out its 65nm process at its 300mm-wafer fabs. He admitted there was currently a "shortage" of some chipsets, built in Intel's 200mm-wafer fabs, but promised that as CPU production moves to 65nm, 90nm 300mm wafer capacity will be freed up for chipsets and "other products".
However, 65nm CPUs are not expected to go into volume production until late Q4, so supply may remain limited for a while yet, forcing Intel to focus on higher-end, higher-margin parts for the time being. ®