Toshiba unveils 1GHz 65nm media processor

Can be customised into a million varieties, apparently

Toshiba today announced what it claims is the world's first 1GHz configurable microprocessor - and probably the first of its kind to be fabbed at 65nm.

The MeP (Media Embedded Processor) chip family is aimed at digital consumer electronics kit and is designed to support a high level of customisation - including the addition of new instructions - prior to manufacturing. The architecture also supports the addition of embedded memory.

The 1GHz version, the MeP-h1, was fabbed at 65nm, though Toshiba was quick to point out that it can be produced using more mature processes, such as 90nm, too. However, the newer process directly helped the company get the clock frequency up to 1GHz, it admitted.

The higher speed was also facilitated by a new nine-stage instruction pipeline, extended from the previous MeP generation's five-stage pipeline. The h1 also features an instruction re-order buffer. The chip is founded upon a 32-bit RISC core. Multiple MePs can be connected to form a single system-on-a-chip.

Toshiba said it will tout the part as the foundation for future "digital media products that require processing of large volume of image and audio data", such as digital TVs and DVD recorders. It plans to use the MeP line in its own products and to license the technology to third-parties.

Curiously, that's also the role that Toshiba has in mind for the Cell processor, which it co-developed with Sony and IBM. Sony, of course, wants Cell for PlayStation 3, but it too has said it plans to build the chip into future consumer electronics product.

Cell is expected to debut running at 3.2GHz, according to comments made by the companies at the HotChips conference this week. Like MeP-h1, Cell is expected to be fabbed at 65nm, but it's likely to run considerably hotter than the 1GHz part, and that well may be the basis on which Toshiba differentiates the two products.

Toshiba also said this week it had developed a Cell companion chip which connects directly to the processor's chip-to-chip bus and provides hardware decoding for up to 48 separate standard-resolution video streams. ®


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