Intel to add memory controllers to future Xeons, Itanics

How to make one chipset support IA-32 and IA-64 CPUs

Intel is to follow AMD's lead and integrate memory controllers onto its x86 server processors, computer maker SGI has claimed.

Speaking to reporters this week, SGI's Senior VP and CTO, Eng Lim Goh, said the unified chipset will also see the memory controller moved from its traditional North Bridge location and onto the processor die.

It's not going to happen until 2007, apparently, but when it comes it will be part of the chip giant's scheme to ship system logic that supports both its Xeon processor range and its Itanium family.

Intel's plan to merge its Xeon and Itanium chipsets goes back to beyond April 2004, when the first hints that it had such a goal in mind emerged. In July 2004, Jason Waxman, then director of multiprocessor marketing for Intel's Enterprise Product Group, now its Digital Enterprise Group, said the company would ship unified chipsets by 2007.

In the past, Intel has been dismissive of moves to put the memory controller on the processor. Its line has always been it makes more sense to leave it on the North Bridge because it's cheaper to upgrade chipset silicon to support new memory technologies than it is to update CPU silicon.

That's one reason why AMD won't have DDR 2 support until next year, though the relative level of demand between DDR and DDR 2 has also played an important rule in the timing of AMD's move to DDR 2. AMD clearly decided it made more sense to wait until it was redesigning the die in any case than to re-spin its existing processors to support a memory technology that's some way from market dominance.

However, shrinking process sizes - by 2007, Intel will be well into 65nm - give the company more transistors to play with, and sooner or later it was going to have to consider bringing North Bridge elements onto the CPU.

The 2007 timeframe puts the emphasis on Intel's 'Tukwila' multi-core Itanium chip, and the 65nm multi-core Xeon part, 'Whitefield', both of which are expected to be the first two members of their respective processor families to utilise the unified interconnection architecture. ®

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