Original URL: http://www.theregister.co.uk/2005/03/18/intel_29_march_potomac/
Intel to ship 'Potomac' Xeon MP this month
64-bit, 8MB L3 cache monster joined by E8500 chipset
Posted in Hardware, 18th March 2005 12:02 GMT
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Intel will ship its 'Potomac' 64-bit Xeon MP processor on 29 March, bundling it with the 'Twin Castle' E8500 chipset into a server platform the company has codenamed 'Truland'.
The chip maker announced mid-February that it would ship (http://www.theregister.co.uk/2005/02/14/intel_xeon_2mb_l2_64-bit/) Potomac "within 90 days", but the more specific launch date comes courtesy of a Techworld report (http://www.techworld.com/opsys/news/index.cfm?NewsID=3318).
The updated Xeon MP processor will contain 8MB of L3 cache, up from the 4MB offered by the current top-of-the-range model, and run at a clock speed of 3.33GHz. That in turn suggests the part will update the current Xeon MP frontside bus speed from 400MHz.
Indeed, the E8500 chipset supports a twin 667MHz bus, Intel has said, the better to cope with future multi-core processors. It is believed to contain a memory controller divorced from the North Bridge, the better to facilitate speedy support for faster memory technologies in the future. At launch E8500 will support 400MHz DDR 2 SDRAM with ECC. It will also provide a PCI Express bus.
Potomac will ship alongside 'Cranford', a cheaper version of the product, equipped with 1MB of L2 cache and designed to fill the gap between two-way Xeon DP-based systems and four-way Xeon MP servers.
Techworld's use of the Truland codename is interesting. At Intel Developer Forum earlier this month, the chip maker disclosed (http://www.theregister.co.uk/2005/03/01/intel_xeon_truland/) the existence of Truland as a Xeon MP platform sure enough, but said it would feature the 'Paxville' processor - its first dual-core Xeon MP, due to be launched later this year but shipping in volume in Q1 2006. Presumably, Intel is now positioning Truland as a broader Xeon MP platform. ®
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