Intel confirms Itanium has a future

Welcome, Richford, Reidland and Poulson

By Ashlee Vance, 2nd March 2005

Magic Quadrant for Enterprise Backup/Recovery

IDF Spring 05 Intel today dished out code-names galore for its future server processors, covering both the Itanium and Xeon product lines.

Many of you will already be familiar with the dual-core version of Itanium called Montecito due out this year. You'll also likely know its follow on named Montvale and a low-end version of the same chip called Millington.

What you haven't heard about before is a chip family called Richford that will cover Itaniums made in 2007 and beyond.

Intel has started to give entire chip families their own code-names, and Richford is the first such family code-name for the Itanium line. It will be made up of the Tukwila chip, first revealed by The Register, and its follow-on called Poulson. Intel executives declined to provide any details about Poulson other than its name. So much for full disclosure.

The Dimona processor will also be part of the Richford family. It's a version of Itanium aimed at two processor servers.

In 2007, Intel will introduce the Reidland family of Xeon processors. The first member of this family will be the Whitefield chip, also first revealed by The Register. It will have multiple processor cores and be designed primarily by Intel's Indian chip design team. Whitefiled should be picked up for use in multiprocessor servers. Our sources indicate it will be the first Xeon chip to make strong use of Intel's mobile technology.

Intel has yet to reveal the code-name for its 2007 Xeon aimed at two-processor servers.

Overall, the flood of code-named released at today's Intel Developer Forum gave proof that Intel intends to keep developing Itanium despite is painfully slow market adoption. "We are dead set on making Itanium a long term winner in the marketplace," said Pat Gelsinger, a senior VP at Intel.

Intel insists that it has yet to firm up details around these future chips. They may have fewer, faster processor cores or more low-power cores.

"The overall theme is more cores per socket," Gelsinger said. ®