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Original URL: http://www.theregister.co.uk/2004/10/06/amd_dual-core_sse3/

AMD dual-core Opterons gain SSE 3 support

By Tony Smith
Published Wednesday 6th October 2004 09:22 GMT

AMD's dual-core AMD64 chips will provide instructions compatible with Intel's SSE 3 technology, the chip maker announced at the Microprocessor Forum yesterday.

SSE 3 debuted with the 90nm Pentium 4 processor, 'Prescott', in February 2004 (http://www.theregister.co.uk/2004/02/02/intel_finally_launches_prescott/). So far, AMD's 64-bit processors support the original Streaming SIMD Extensions and SSE 2 through updates to the company's 3DNow! technology, but this is the first indication that the chips are to gain SSE 3 support.

However, the Opteron will offer only ten SSE 3 instructions.

Since the dual-core Opteron is based on AMD's 90nm Opteron, it's possible that this part, which is due to ship shortly, will also support SSE 3, as may the 90nm Athlon 64.

AMD's Forum presentation also revealed the dual-core Opteron, which the company has already said is due to ship mid-2005, will contain 205m transistors. Its 90nm fabrication means that together, the two cores and ancillary circuitry will take up no more space than a 130nm single-core Opteron.

The upcoming chip, which will have a 940-pin interface, will have a 95W power envelope.

The two cores will together operate in a symmetric multiprocessing mode, so the OS sees them as two distinct processors. At this stage it's not clear whether they will also be able to operate asymmetrically, in order to run two operating systems, one per core, or two separate instances of the same OS.

That's certainly going to be a feature of Freescale's upcoming e600-based dual-core PowerPC (http://www.theregister.co.uk/2004/09/28/freescale_g4_7448/) chip, and may well be the basis for Intel's upcoming Silvervale and Vanderpool partitioning and virtualisation technologies.

Each Opteron core will contains its own 1MB L2 cache. The two cores connect to a combined system request interface and crossbar switch, and on to the chip's dual-channel 128-bit DDR SDRAM memory controller and three HyperTransport links. AMD said it has improved the chip's hardware pre-fetch sub-system. ®

Related stories

AMD heralds OS support for dual-core CPUs (http://www.theregister.co.uk/2004/09/07/amd_dual-core_support/)
AMD to demo dual-core Opteron box (http://www.theregister.co.uk/2004/08/31/amd_dual-core_demo/)
AMD could ship a quad-core Opteron on 2007 (http://www.theregister.co.uk/2004/08/16/amd_quad-core_opteron/)
Freescale to launch 90nm PowerPC G4 today (http://www.theregister.co.uk/2004/09/28/freescale_g4_7448/)
Freescale to detail dual-core PowerPC G4 (http://www.theregister.co.uk/2004/08/18/dual-cores_detailed/)
Intel to bring server-style virtualisation to desktop chips (http://www.theregister.co.uk/2003/09/16/intel_to_bring_serverstyle_virtualisation/)
Intel admits Itanium pains, plots server future (http://www.theregister.co.uk/2004/09/08/intel_whitefield_arrives/)

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