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Intel ships 'execute disable' Pentium 4s

Socket T Celerons arrive, too

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Intel yesterday introduced its first desktop processors to support what it calls Execute Disable Bit (EDB) technology - essentially the same code-disabling technology found in AMD, Transmeta and other CPUs, and used by Windows XP Service Pack 2 to render some viruses ineffective.

The update was expected: Intel documents seen by The Register in July 2004 pinpointed a Q4 release of EDB-enabled P4s and Celerons.

The chip giant also introduced its first Socket T Celeron chips.

Intel's EDB-enabled processors include both new and old models. All of them are indicated by a 'J' after the CPU model number.

The technology is now incorporated into all 90nm, Socket T Pentium 4 5xx processors, from the 520 to the 560, through a new core version, E-0. Older versions, based on the D-0 core, are still available alongside the E-0 parts. Prices remain unchanged: the 520 and 520J are $163; the 530 and 530J, $178; the 540 and 540J, $218; the 550 and 550J, $278; and the 560 and 560J, $417;

The first 775-pin Socket T Celerons are the 325J, 330J, 335J and340J, clocked at 2.53, 2.66, 2.80 and 2.93GHz, respectively. Again, they're priced to match the existing, EDB-less parts: $79, $83, $103 and $117, respectively.

The 340J is a new clock speed for the Celeron desktop line, and was accompanied by a second new model, the 340.

Intel's 90nm mobile Celeron M 350 and 360 also made an appearance on the company's price list yesterday, at $107 and $134, respectively. So did the already announced $262 Mobile Pentium 4 548.

Next up for a 'J' release is Intel's 64-bit Xeon DP chip, 'Nocona'. These were expected to have made an appearance at the end of September, but as yet they have not been added to Intel's official price list.

EDB allows the CPU to be set not to run code stored in 'data-only' sections of memory. That, it's hoped, will block a number of viruses that hide within such areas of RAM. ®

Related stories

Intel to add NX security to Pentium 4 in Q4
Intel 'Nocona' Xeon to get 'no execute' support
Intel grows Socket T Celeron line-up

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