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Intel to cut Prescott leakage by 75% at 65nm

'On track' for 2005 delivery

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Intel has pledged to reduce drastically leakage effects in its 65nm process, having punched out its first device containing over 500m transistors using the technology.

Leakage has proved something of a problem for Intel's 90nm process following the shift down from 130nm chip production. While smaller transistor ought to consume less power, their more compact size also increases the opportunity for current to leak through, forcing chip makers to up the power in order to get each transistor to operate efficiently.

That's why a 90nm Pentium 4 consumes more power than a 130nm version, not less. However, according to Intel, its 65nm process will "cut leakage by four times at constant performance compared to 90nm transistors", presumably its own ones.

The secret? The chip giant's strained silicon technique. It used strained silicon in its 90nm process, of course, but a "second generation" will be used at the 65nm node to "increase transistor performance by 10-15 per cent without increasing leakage".

The process also makes use of a low-k dielectric insulator, which further limits leakage. The process uses copper interconnects, arranged in eight layers.

All of which suggests that not only will 65nm transistors be physically smaller than their 90nm equivalents, but they will consume less power and leak less current, too.

Intel also said it has implemented a technique that shuts off the flow of current to unused banks of transistors, to reduce power consumption further. That may well be advantageous in a memory device, but it remains to be seen how applicable it is to a more active device like a microprocessor.

Intel bases this claim on the 70Mb SRAM chips it has been fabbing at 65nm at its Hillsboro, Oregon 300mm-wafer development fab. It's not the first 65nm part Intel has produced - in November 2003, it turned out a working 4Mb SRAM chip.

The chip giant declared itself "on track" to deliver its 65nm technology next year, but processors fabbed at that size are unlikely to ship in volume before the very end of 2005.

We've heard this kind of thing before, of course, when Intel was touting its 90nm process, so it's important not to get too carried away by Intel's Moore's law boosterisms. Most chip makers talk up processes when their still in the lab - shipping working product is another matter, as Intel initially found with its 90nm chips, as did IBM. AMD finds itself at just such a point today - will its 90nm process perform as forecast, or will leakage and yield issues cause it all sorts of bother.

Intel will itself face such questions next year when it begins the shift from 90nm to 65nm - as will its rivals. And the chip giant is predicating much of its future strategic technologies - multi-core CPUs, LaGrange security hardware, and the ability to run multiple operating systems on the same processor, simultaneously - on the success of its 65nm process. ®

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