IBM eFuse to yield self-repairing, self-regulating CPUs
Mighty Morphin' PowerPCs
IBM's Power 5 processor cores will be able automatically to repair and remodel themselves - albeit in a limited way - to improve their performance and power consumption characteristics.
So claims Big Blue, which this weekend said Power 5 and other upcoming processors will feature what it calls a "breakthrough chip morphing technology".
Said technology will ship under the name eFuse, so called because it employs millions of electrical fuses that are built into the chip's circuitry. Together, the microfuses act as a kind of autonomous traffic control network, responding to the changing demands placed on the microprocessor to switch individual circuits on and off as required.
Under-utilised circuits can be throttled back to conserve power - a technique already used in modern processors, albeit on a larger functional unit-level scale - which in-demand circuits can be adjusted upward to enhance performance, IBM said.
The traffic management analogy is also IBM's. It likens the technology to opening and closing a highway's lanes according to the level of traffic. Of course, you can't open up lanes that aren't there in the first place, so the analogy implies the addition of resources on board each die the remain unused except in times of peak demand.
Certainly Power 5 is known to support simultaneous multi-threading (SMT), the same technique that Intel uses but calls HyperThreading. Essentially, functional units unneeded by one thread are given a second thread to process, with the upshot that the OS 'sees' the CPU as two, rather than one. You don't get a doubling of performance, but there is a gain.
By the sounds of things, IBM has rolled its SMT implementation into the broader eFuse technology, which also appears to provide a number of features originally came out of Big Blue's eLiza project, which sought to develop fault detection and management systems for software and hardware.
Indeed, "eFuse is part of a built-in self-repair system that constantly monitors a chip's functionality. If an imperfection is detected, this technology 'instinctively' initiates corrective actions by tripping inexpensive electrical fuses that are designed into the chip. The fuses help the chip control individual circuit speed to manage power consumption and repair unexpected, and potentially costly flaws", says IBM.
"If the technology detects that the chip is malfunctioning because individual circuits are running too fast or too slow, it can 'throttle down' these circuits or speed them up by controlling the appropriate local voltage," the company continues. So, overclockers, beware.
eFuse appears to operate at several levels. There's an element of pre-ship tuning, in which IBM allows eFuse to adapt processors for the customer's anticipated application load. On site, the technology continues to adapt according to ongoing workloads.
So how does is work? Essentially, the system uses the phenomenon of 'electromigration', in which moving electrons - current - transfer momentum to the surrounding crystal lattice. That causes the lattice to vibrate and can ultimately induce changes in the microstructure that in turn cause a circuit to fail - the chip equivalent of a light-bulb filament fusing. The greater the vibrations, the hotter the circuit and the hotter the circuit gets, the more it vibrates and the more likely electrons are to hit the lattice, imparting more momentum.
This is a real problem with integrated circuits, and chip designers have spent many hours and dollars figuring out how to limit the problem and thus be able to ship chips that don't fail after a few weeks' operation.
IBM claims that it is the first to actually use this unwanted phenomenon to control all those fuses it's added to the chip, presumably by using the thermal changes to trip fuses and thus kick in so-far unused circuits. Again, that implies a high level of redundancy.
IBM admits the technique isn't entirely new, but it has figured out how to trip the fuses without damaging other parts of the processor, which was the key failing of previous attempts to use microfuses.
In addition to Power 5, IBM will add eFuse to all other 90nm chips it produces, including future PowerPC G5s, the company's literature suggests. It will also offer the technique to foundry customers. ®
UMC techies boost SOI chip speed by 30%
IBM and Stanford's spintronics revolution
IBM fabs 90nm G5 using strained silicon
AMD to offer strained silicon chips
IBM boffins stretch silicon to speed chips 35%
IBM boffins boost combo computing, wireless chips
IBM boffins boost chip performance by 65%
AMD 'super' SOI to boost chip speeds by 30%
Motorola mixes silicon, gallium arsenide for super-chips
IBM preps 210GHz chip technology
Sponsored: Today’s most dangerous security threats