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Intel 'Nocona' Xeon to get 'no execute' support

Core update due late September

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Intel will ship Xeon processors capable of supporting Windows XP Service Pack 2 Data Execution Prevention (DEP) security feature from 24 September, company documents seen by The Register reveal.

On Monday, Intel will begin shipping its 90nm 'Nocona' Xeon DP chip. Derived from the 'Prescott' Pentium 4, Nocona will support an 800MHz frontside bus speed and be made available in clock frequencies from 2.8GHz to 3.6GHz. The chips contain 1MB of L2 cache. They also support Intel's AMD64-like 64-bit x86 instruction set extensions, EM64.

Monday's parts will be based on the chip's D-0 core. But just as Intel is upgrading the D-0 P4 core to version E-0, so too will the new Xeon get a similar upgrade.

But while E-0 P4s are scheduled to arrive early October, the E-0 Xeons will ship a few weeks ahead of them, in late September.

According to the Intel documentation, the Xeon E-0 stepping provides support for the "execution disable bit", which is the hardware foundation upon which WinXP SP2's DEP is built. Essentially, it prevents executable code running when it's located in a page of memory earmarked for data. AMD's CPUs have had the feature for some time - AMD calls it 'No-execute Page Protection', or NX for short - and Transmeta is building it into the 90nm version of its Efficeon x86-compatible CPU.

The P4 is expected to gain DEP support in Q4 2004, but at this stage, it's not clear whether the feature will come from the E-0 stepping. Intel's P4 documentation doesn't say so, but the technology's incorporation into the 90nm Xeon suggests it could well be.

However, the anticipated timing of a P4 with the "execution disable bit" provision coincided with the original timeframe for the 4GHz P4. That part has been put back to Q1 2005, Intel has admitted, which could also push back DEP support.

The Xeon E-0 stepping will also "incorporate planned power optimisations to enable speed enhancements", including Thermal Monitor 2 and an enhanced processor halt state. ®

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