Feeds

UMC techies boost SOI chip speed by 30%

Use unwanted quantum tunnelling effects

  • alert
  • submit to reddit

Boffins at UMC, the world's second largest chip foundry, have figured out how to use quantum tunnelling to improve the performance of silicon-on-insulator (SOI) transistors.

UMC dubs the new technique Direct Tunneling Floating-Body Potential (DTFBP) and claimed today it gives PMOS transistors a 30 per cent higher drive current over standard SOI elements.

Crucially, the company said, using DTFBP doesn't make the fabrication process any more complex - unlike strained silicon, for example, which requires big tweaks to be made to chip production lines.

Intel is using strained silicon for its 90nm process, and IBM is using the technique to improve its own 90nm SOI chips. So too is AMD.

Tunnelling is the quantum mechanical phenomenon by which an electron can pass through a energy barrier it ought not to be able to traverse due to insufficient energy of its own.

As transistors get smaller and smaller, such effects play an increasingly important role in chip design. Tunnelling usually manifests itself as electrons passing through thin layers of insulating material. This 'leakage' is bad. SOI transistors are susceptible to the problem because they are mounted - with good reason: it lowers transistor capacitance, thus improving its operation as a voltage-controlled switch - on an insulator.

A downside of SOI is the so-called 'floating-body effect', which results in erratic transistor behaviour - it causes early source-to-drain breakdown, in the jargon - when the supply voltage is reduced. UMC's system tweaks the transistor structure to manipulate the effect of tunnelling to prevent the floating-body effect.

The UMC team behind the discovery published details of their findings in April via the IEEE. You can find the paper here. ®

Related stories

Silicon on insulator key to AMD 90nm success - analyst
IBM boffins boost combo computing, wireless chips
IBM boffins boost chip performance by 65%
AMD to offer strained silicon chips
IBM fabs 90nm G5 using strained silicon
AMD dismisses Intel high-k transistor tech
Intel claims high-k material will slash chip power hunger
AMD and Intel scientists outline future chip tech
AMD super SOI to boost chip speeds by 30%
IBM, AMD unveil terahertz transistor breakthroughs

Whitepapers

Forging a new future with identity relationship management
Learn about ForgeRock's next generation IRM platform and how it is designed to empower CEOS's and enterprises to engage with consumers.
Why cloud backup?
Combining the latest advancements in disk-based backup with secure, integrated, cloud technologies offer organizations fast and assured recovery of their critical enterprise data.
Win a year’s supply of chocolate
There is no techie angle to this competition so we're not going to pretend there is, but everyone loves chocolate so who cares.
High Performance for All
While HPC is not new, it has traditionally been seen as a specialist area – is it now geared up to meet more mainstream requirements?
Intelligent flash storage arrays
Tegile Intelligent Storage Arrays with IntelliFlash helps IT boost storage utilization and effciency while delivering unmatched storage savings and performance.