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IBM to fab next-gen VIA CPU

90nm process to take Esther beyond 2GHz

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VIA will use IBM's 300mm East Fishkill wafer fab - the foundry already used to punch out CPUs for Apple and Nvidia, and soon Microsoft and Sony - to produce the next generation of its x86 processor family. The company will utilise Big Blue's 90nm silicon-on-insulator, low-k dielectric process.

The new chip core, officially dubbed the C5J and codenamed 'Esther', will be pitched at low-power applications - hence the interest in SOI. VIA said Esther will consume just 3.5W at 1GHz, but the chip is designed to clock to 2GHz and beyond.

Esther will build on the data security features of today's 130nm C3 chips, which accelerated AES encryption and provides a true random number generator. Esther will add RSA encryption (with Montgomery Multiplier support) and Secure Hashing (SHA-1 and SHA-256) acceleration, VIA said today.

The new chip will also support the No Execution (NX) feature of Windows XP Service Pack 2 that is intended to prevent code held in data-only memory blocks from being run. That's an approach taken by many viruses and worms. Microsoft hopes NX will severely curtail the threat from these rogue programs.

Esther will operate using an 800MHz frontside bus. It will include support for Intel's SSE 2 and 3 multimedia-oriented instruction sets. The chip will get a larger L2 cache. The C3 has 64KB of L2 - its designers have traditionally favoured a large, 128KB L1 cache. VIA didn't say how much larger the C5J's caches will be, but with a 90nm process there's room to beef it up considerably if they choose.

VIA did not provide availability information. ®

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