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First dual-core Itanic to sport 24MB of cache

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Intel's first dual-core Itanic, 'Montecito', will sport a whopping 24MB of L3 cache, the chip giant said yesterday, by way of Reuters.

And in a staggering feat of processor engineering that has clearly wowed the news agency's hacks, the chip will "be able to run several applications at once".

Gosh. If only we could do that now...

Intel announced that Montecito would contain two processing cores early in the year, and was reiterated more publicly in September, at Intel Developer Forum. The chip will be formed from more than one billion transistors and ship sometime in 2005, Intel president Paul Otellini said.

A good proportion of that one billion transistor budget will clearly be spent on the cache, though whether the two cores share it or have 12MB a piece isn't known. Either way, each will have access to at least twice the L3 cache of today's 'Madison' Itanium 2s.

Madisons with 9MB are roadmapped to ship next year. They will also offer higher clock frequencies that the current Itanic 2's maximum, 1.5GHz.

Come 2005, and Montecito will have to compete with dual-core AMD Opterons. AMD has said it will ship dual-core Opterons by the end of 2005. Indeed, its 64-bit Hammer architecture was designed specifically with dual-core chips in mind. ®

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